// ******************************************************************************
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  hva_peh_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2021/04/08 19:34:52 Create file
// ******************************************************************************

#ifndef HVA_PEH_C_UNION_DEFINE_H
#define HVA_PEH_C_UNION_DEFINE_H

/* Define the union csr_pcihdr_id_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_vendor_id : 16; /* [15:0] */
        u32 hdr_device_id : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_id_u;

/* Define the union csr_pcihdr_cmdsts_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_io_space_en : 1;      /* [0] */
        u32 hdr_mem_space_en : 1;     /* [1] */
        u32 hdr_bus_master_en : 1;    /* [2] */
        u32 hdr_special_cycle_en : 1; /* [3] */
        u32 hdr_mem_wr_invld_en : 1;  /* [4] */
        u32 hdr_vga_snoop_en : 1;     /* [5] */
        u32 hdr_parity_err_resp : 1;  /* [6] */
        u32 hdr_idsel_stepping : 1;   /* [7] */
        u32 hdr_serr_en : 1;          /* [8] */
        u32 hdr_fast_b2b_en : 1;      /* [9] */
        u32 hdr_intx_disable : 1;     /* [10] */
        u32 hdr_rved : 8;             /* [18:11] */
        u32 hdr_intx_status : 1;      /* [19] */
        u32 hdr_cap_list : 1;         /* [20] */
        u32 hdr_66mhz_cap : 1;        /* [21] */
        u32 hdr_0reserved : 1;        /* [22] */
        u32 hdr_fastb2b_cap : 1;      /* [23] */
        u32 hdr_mdata_par_err : 1;    /* [24] */
        u32 hdr_devsel_timing : 2;    /* [26:25] */
        u32 hdr_sig_target_abort : 1; /* [27] */
        u32 hdr_rx_target_abort : 1;  /* [28] */
        u32 hdr_rx_master_abort : 1;  /* [29] */
        u32 hdr_rx_sys_err : 1;       /* [30] */
        u32 hdr_deteted_par_err : 1;  /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_cmdsts_u;

/* Define the union csr_pcihdr_clsrev_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_revision_id : 8;     /* [7:0] */
        u32 hdr_program_inf : 8;     /* [15:8] */
        u32 hdr_sub_class_code : 8;  /* [23:16] */
        u32 hdr_base_class_code : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_clsrev_u;

/* Define the union csr_pcihdr_misc_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_cachlie_size : 8;  /* [7:0] */
        u32 hdr_latency_timer : 8; /* [15:8] */
        u32 hdr_header_type : 7;   /* [22:16] */
        u32 hdr_multfunc_dev : 1;  /* [23] */
        u32 hdr_bist_result : 4;   /* [27:24] */
        u32 hdr_1reserved : 2;     /* [29:28] */
        u32 hdr_start_bist : 1;    /* [30] */
        u32 hdr_bist_cap : 1;      /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_misc_u;

/* Define the union csr_pcihdr_bar0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_bar0_type : 1;        /* [0] */
        u32 hdr_bar0_reserved : 1;    /* [1] */
        u32 hdr_bar0_width : 1;       /* [2] */
        u32 hdr_bar0_prefetch_en : 1; /* [3] */
        u32 hdr_2reserved : 9;        /* [12:4] */
        u32 hdr_bar0_addr : 19;       /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_bar0_u;

/* Define the union csr_pcihdr_bar1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_bar1_type : 1;        /* [0] */
        u32 hdr_bar1_reserved : 1;    /* [1] */
        u32 hdr_bar1_width : 1;       /* [2] */
        u32 hdr_bar1_prefetch_en : 1; /* [3] */
        u32 hdr_bar1_2reserved : 19;  /* [22:4] */
        u32 hdr_bar1_addr : 9;        /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_bar1_u;

/* Define the union csr_pcihdr_bar2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_bar2_type : 1;        /* [0] */
        u32 hdr_bar2_reserved : 1;    /* [1] */
        u32 hdr_bar2_width : 1;       /* [2] */
        u32 hdr_bar2_prefetch_en : 1; /* [3] */
        u32 hdr_bar2_2reserved : 13;  /* [16:4] */
        u32 hdr_bar2_addr : 15;       /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_bar2_u;

/* Define the union csr_pcihdr_bar3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_bar3_type : 1;        /* [0] */
        u32 hdr_bar3_reserved : 1;    /* [1] */
        u32 hdr_bar3_width : 1;       /* [2] */
        u32 hdr_bar3_prefetch_en : 1; /* [3] */
        u32 hdr_bar3_2reserved : 14;  /* [17:4] */
        u32 hdr_bar3_addr : 14;       /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_bar3_u;

/* Define the union csr_pcihdr_bar4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_bar4_type : 1;        /* [0] */
        u32 hdr_bar4_reserved : 1;    /* [1] */
        u32 hdr_bar4_width : 1;       /* [2] */
        u32 hdr_bar4_prefetch_en : 1; /* [3] */
        u32 hdr_bar4_2reserved : 18;  /* [21:4] */
        u32 hdr_bar4_addr : 10;       /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_bar4_u;

/* Define the union csr_pcihdr_bar5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_bar5_addr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_bar5_u;

/* Define the union csr_pcihdr_cbus_ptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_carbus_cis_ptr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_cbus_ptr_u;

/* Define the union csr_pcihdr_subsys_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_sys_vendor_id : 16; /* [15:0] */
        u32 hdr_sub_sys_id : 16;    /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_subsys_u;

/* Define the union csr_pcihdr_exprwm_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_ext_rom_enable : 1;     /* [0] */
        u32 hdr_6reserved : 10;         /* [10:1] */
        u32 hdr_ext_rom_base_addr : 21; /* [31:11] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_exprwm_u;

/* Define the union csr_pcihdr_capptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_cap_ptr : 8;    /* [7:0] */
        u32 hdr_7reserved : 24; /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_capptr_u;

/* Define the union csr_pci_rsvd_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_8reserved : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pci_rsvd_u;

/* Define the union csr_pcihdr_int_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hdr_int_line : 8;    /* [7:0] */
        u32 hdr_int_pin : 8;     /* [15:8] */
        u32 hdr_3creserved : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcihdr_int_u;

/* Define the union csr_pcie_capability_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_pci_capid : 8;      /* [7:0] */
        u32 pcap_nxt_ptr : 8;        /* [15:8] */
        u32 pcap_pci_cap_ver : 4;    /* [19:16] */
        u32 pcap_port_type : 4;      /* [23:20] */
        u32 pcap_slot_implement : 1; /* [24] */
        u32 pcap_int_msg_num : 5;    /* [29:25] */
        u32 pcap_15reserved : 2;     /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie_capability_header_u;

/* Define the union csr_device_capbility_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_max_payload_size_support : 3; /* [2:0] */
        u32 pcap_phanotom_fun_sup : 2;         /* [4:3] */
        u32 pcap_ext_tag_sup : 1;              /* [5] */
        u32 pcap_ep_l0s_accept_lat : 3;        /* [8:6] */
        u32 pcap_ep_l1_accept_lat : 3;         /* [11:9] */
        u32 pcap_undefine_04 : 3;              /* [14:12] */
        u32 pcap_ro_base_err_rpt : 1;          /* [15] */
        u32 pcap_0reserved : 2;                /* [17:16] */
        u32 pcap_cap_slot_pwr_limit_val : 8;   /* [25:18] */
        u32 pcap_cap_slot_pwr_sca : 2;         /* [27:26] */
        u32 pcap_flr_cap : 1;                  /* [28] */
        u32 pcap_16reserved : 3;               /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_device_capbility_u;

/* Define the union csr_device_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_cor_err_rpt_en : 1;      /* [0] */
        u32 pcap_non_fat_rpt_en : 1;      /* [1] */
        u32 pcap_fat_err_rpt_en : 1;      /* [2] */
        u32 pcap_ur_rpt_en : 1;           /* [3] */
        u32 pcap_relax_order_en : 1;      /* [4] */
        u32 pcap_max_payload_size : 3;    /* [7:5] */
        u32 pcap_extend_tag_en : 1;       /* [8] */
        u32 pcap_phatom_func_en : 1;      /* [9] */
        u32 pcap_aux_pwr_pm_en : 1;       /* [10] */
        u32 pcap_no_snoop_en : 1;         /* [11] */
        u32 pcap_max_read_req_size : 3;   /* [14:12] */
        u32 pcap_init_flr_reset_rwwo : 1; /* [15] */
        u32 pcap_cor_err_detect : 1;      /* [16] */
        u32 pcap_non_fata_detect : 1;     /* [17] */
        u32 pcap_fat_err_detect : 1;      /* [18] */
        u32 pcap_ur_detect : 1;           /* [19] */
        u32 pcap_aux_pwr_detect : 1;      /* [20] */
        u32 pcap_tlp_pending : 1;         /* [21] */
        u32 pcap_1reserved : 10;          /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_device_ctrl_status_u;

/* Define the union csr_link_capbility_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_max_link_speed : 4;          /* [3:0] */
        u32 pcap_max_link_width : 6;          /* [9:4] */
        u32 pcap_aspm_sup : 2;                /* [11:10] */
        u32 pcap_l0_exit_lat : 3;             /* [14:12] */
        u32 pcap_l1_exit_lat : 3;             /* [17:15] */
        u32 pcap_clock_pm : 1;                /* [18] */
        u32 pcap_surprise_dn_err_rpt_cap : 1; /* [19] */
        u32 pcap_dl_link_act_rpt_cap : 1;     /* [20] */
        u32 pcap_link_band_notice_cap : 1;    /* [21] */
        u32 pcap_aspm_opt_compliance : 1;     /* [22] */
        u32 pcap_1reserved : 1;               /* [23] */
        u32 pcap_port_num : 8;                /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_link_capbility_u;

/* Define the union csr_link_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_aspm_ctrl : 2;             /* [1:0] */
        u32 pcap_4reserved : 1;             /* [2] */
        u32 pcap_rcb : 1;                   /* [3] */
        u32 pcap_link_disable : 1;          /* [4] */
        u32 pcap_retrain_link : 1;          /* [5] */
        u32 pcap_common_clk_cfg : 1;        /* [6] */
        u32 pcap_extended_sync : 1;         /* [7] */
        u32 pcap_clock_pm_en : 1;           /* [8] */
        u32 pcap_hw_auto_width_dis : 1;     /* [9] */
        u32 pcap_link_band_int_en : 1;      /* [10] */
        u32 pcap_link_auto_band_int_en : 1; /* [11] */
        u32 pcap_3reserved : 4;             /* [15:12] */
        u32 pcap_mac_cur_link_spped : 4;    /* [19:16] */
        u32 pcap_mac_cur_link_width : 6;    /* [25:20] */
        u32 pcap_undefined_12 : 1;          /* [26] */
        u32 pcap_link_training : 1;         /* [27] */
        u32 pcap_slot_clk_cfg : 1;          /* [28] */
        u32 pcap_dl_cfg_link_active : 1;    /* [29] */
        u32 pcap_link_band_status : 1;      /* [30] */
        u32 pcap_link_auto_band_status : 1; /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_link_ctrl_status_u;

/* Define the union csr_slot_capability_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_att_button_pre : 1;       /* [0] */
        u32 pcap_pwr_ctrl_pre : 1;         /* [1] */
        u32 pcap_msl_sensor_pre : 1;       /* [2] */
        u32 pcap_att_indecator_pre : 1;    /* [3] */
        u32 pcap_pwr_indicator_pre : 1;    /* [4] */
        u32 pcap_hot_plug_surprise : 1;    /* [5] */
        u32 pcap_hot_plug_cap : 1;         /* [6] */
        u32 pcap_slot_pwr_limit_val : 8;   /* [14:7] */
        u32 pcap_slot_pwr_limit_scale : 2; /* [16:15] */
        u32 pcap_elec_interlock_pre : 1;   /* [17] */
        u32 pcap_no_comman_cpled_sup : 1;  /* [18] */
        u32 pcap_physical_slot_num : 13;   /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_slot_capability_u;

/* Define the union csr_slot_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_att_buttom_pre_en : 1;      /* [0] */
        u32 pcap_pwr_fault_det_en : 1;       /* [1] */
        u32 pcap_mrl_sensor_change_en : 1;   /* [2] */
        u32 pcap_presence_det_change_en : 1; /* [3] */
        u32 pcap_command_cpled_int_en : 1;   /* [4] */
        u32 pcap_hot_plug_int_en : 1;        /* [5] */
        u32 pcap_att_indicator_ctrl : 2;     /* [7:6] */
        u32 pcap_pwr_indicator_ctrl : 2;     /* [9:8] */
        u32 pcap_pwr_ctrled_ctrl : 1;        /* [10] */
        u32 pcap_elec_interlock_ctrl : 1;    /* [11] */
        u32 pcap_dl_state_change_en : 1;     /* [12] */
        u32 pcap_6reserved : 3;              /* [15:13] */
        u32 pcap_attention_button : 1;       /* [16] */
        u32 pcap_pwr_fault_det : 1;          /* [17] */
        u32 pcap_mrl_sensor_change : 1;      /* [18] */
        u32 pcap_presencd_det_change : 1;    /* [19] */
        u32 pcap_command_cpled : 1;          /* [20] */
        u32 pcap_mrl_sensor_st : 1;          /* [21] */
        u32 pcap_presencd_det_st : 1;        /* [22] */
        u32 pcap_elec_interlock_st : 1;      /* [23] */
        u32 pcap_dl_state_change : 1;        /* [24] */
        u32 pcap_5reserved : 7;              /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_slot_ctrl_status_u;

/* Define the union csr_root_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_7reserved : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_root_ctrl_status_u;

/* Define the union csr_root_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_pme_rid : 16;    /* [15:0] */
        u32 pcap_pme_status : 1;  /* [16] */
        u32 pcap_pme_pending : 1; /* [17] */
        u32 pcap_8reserved : 14;  /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_root_status_u;

/* Define the union csr_device_capability2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_cpl_timeout_range : 4;       /* [3:0] */
        u32 pcap_cpl_timeout_disable_sup : 1; /* [4] */
        u32 pcap_ari_fwd_sup : 1;             /* [5] */
        u32 pcap_atomicop_route_sup : 1;      /* [6] */
        u32 pcap_atomic_32bit_cpl_sup : 1;    /* [7] */
        u32 pcap_atomic_64bit_cpl_sup : 1;    /* [8] */
        u32 pcap_cas_128bit_cpl_sup : 1;      /* [9] */
        u32 pcap_no_roen_prpr_pass : 1;       /* [10] */
        u32 pcap_ltr_mech_sup : 1;            /* [11] */
        u32 pcap_tph_cpl_sup : 2;             /* [13:12] */
        u32 pcap_ln_sys_cls : 2;              /* [15:14] */
        u32 pcap_sup_10bit_cpl_tag : 1;       /* [16] */
        u32 pcap_sup_10bit_req_tag : 1;       /* [17] */
        u32 pcap_obff_sup : 2;                /* [19:18] */
        u32 pcap_ext_fmt_sup : 1;             /* [20] */
        u32 pcap_end_end_pfx_sup : 1;         /* [21] */
        u32 pcap_max_end_end_pfx : 2;         /* [23:22] */
        u32 pcap_9reserved : 7;               /* [30:24] */
        u32 pcap_frs_sup : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_device_capability2_u;

/* Define the union csr_device_ctrl2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_cpl_timeout_value : 4;   /* [3:0] */
        u32 pcap_cpl_timeout_dis : 1;     /* [4] */
        u32 pcap_ari_fwd_en : 1;          /* [5] */
        u32 pcap_atomicop_req_en : 1;     /* [6] */
        u32 pcap_atomicop_egress_blk : 1; /* [7] */
        u32 pcap_ido_req_en : 1;          /* [8] */
        u32 pcap_ido_cpl_en : 1;          /* [9] */
        u32 pcap_ltr_mech_en : 1;         /* [10] */
        u32 pcap_en_10bit_req_tag : 1;    /* [11] */
        u32 pcap_11reserved : 1;          /* [12] */
        u32 pcap_obff_en : 2;             /* [14:13] */
        u32 pcap_end_end_pfx_blk : 1;     /* [15] */
        u32 pcap_10reserved : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_device_ctrl2_u;

/* Define the union csr_link_capability2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_13reserved : 1;               /* [0] */
        u32 pcap_link_speed_sup : 7;           /* [7:1] */
        u32 pcap_cross_link_sup : 1;           /* [8] */
        u32 pcap_cfg_tx_lower_skp_cap : 7;     /* [15:9] */
        u32 pcap_cfg_rx_lower_skp_cap : 7;     /* [22:16] */
        u32 pcap_retimer_presence_detect : 1;  /* [23] */
        u32 pcap_retimer2_presence_detect : 1; /* [24] */
        u32 pcap_12reserved : 6;               /* [30:25] */
        u32 pcap_drs_sup : 1;                  /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_link_capability2_u;

/* Define the union csr_link_ctrl_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_target_link_speed : 4;        /* [3:0] */
        u32 pcap_enter_compliance : 1;         /* [4] */
        u32 pcap_hw_auto_speed_dis : 1;        /* [5] */
        u32 pcap_selectable_de_emphasis : 1;   /* [6] */
        u32 pcap_transmit_margin : 3;          /* [9:7] */
        u32 pcap_enter_mod_compliance : 1;     /* [10] */
        u32 pcap_compliance_sos : 1;           /* [11] */
        u32 pcap_compliance_preset_deemp : 4;  /* [15:12] */
        u32 pcap_cur_deemp_level : 1;          /* [16] */
        u32 pcap_eq_8g_complete : 1;           /* [17] */
        u32 pcap_eq_8g_phase1_success : 1;     /* [18] */
        u32 pcap_eq_8g_phase2_success : 1;     /* [19] */
        u32 pcap_eq_8g_phase3_success : 1;     /* [20] */
        u32 pcap_link_8g_eq_req : 1;           /* [21] */
        u32 pcap_retimer_presence_detect : 1;  /* [22] */
        u32 pcap_retimer2_presence_detect : 1; /* [23] */
        u32 pcap_14reserved : 4;               /* [27:24] */
        u32 pcap_dwstm_component_presence : 1; /* [28] */
        u32 pcap_drs_msg_recved : 3;           /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_link_ctrl_status2_u;

/* Define the union csr_slot_cap_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_slot_cap_2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_slot_cap_2_u;

/* Define the union csr_slot_ctrl_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcap_slot_ctrl_2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_slot_ctrl_2_u;

/* Define the union csr_msi_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msicap_capability_id : 8; /* [7:0] */
        u32 msicap_nxt_ptr : 8;       /* [15:8] */
        u32 msicap_enable : 1;        /* [16] */
        u32 msicap_mmc : 3;           /* [19:17] */
        u32 msicap_mme : 3;           /* [22:20] */
        u32 msicap_c64 : 1;           /* [23] */
        u32 msicap_pvm : 1;           /* [24] */
        u32 msicap_support : 7;       /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msi_cap_header_u;

/* Define the union csr_msi_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msicap_0reserved : 2; /* [1:0] */
        u32 msicap_addr : 30;     /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msi_addr_u;

/* Define the union csr_msi_up_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msicap_uaddr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msi_up_addr_u;

/* Define the union csr_msi_data_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msicap_data : 16;      /* [15:0] */
        u32 msicap_1reserved : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msi_data_u;

/* Define the union csr_msi_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msicap_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msi_mask_u;

/* Define the union csr_msi_pending_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msicap_pend : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msi_pending_u;

/* Define the union csr_msix_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msixcap_capability_id : 8; /* [7:0] */
        u32 msixcap_nxt_ptr : 8;       /* [15:8] */
        u32 msixcap_table_size : 11;   /* [26:16] */
        u32 msixcap_0reserved : 3;     /* [29:27] */
        u32 msixcap_func_mask : 1;     /* [30] */
        u32 msixcap_enable : 1;        /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msix_cap_header_u;

/* Define the union csr_msix_table_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msixcap_table_bir : 3;    /* [2:0] */
        u32 msixcap_table_ofset : 29; /* [31:3] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msix_table_u;

/* Define the union csr_msix_pba_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msixcap_pba_bir : 3;    /* [2:0] */
        u32 msixcap_pba_ofset : 29; /* [31:3] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msix_pba_u;

/* Define the union csr_pme_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pmcap_capability_id : 8;   /* [7:0] */
        u32 pmcap_nxt_ptr : 8;         /* [15:8] */
        u32 pmcap_version : 3;         /* [18:16] */
        u32 pmcap_clk : 1;             /* [19] */
        u32 pmcap_0reserved : 1;       /* [20] */
        u32 pmcap_device_spec_ini : 1; /* [21] */
        u32 pmcap_aux_current : 3;     /* [24:22] */
        u32 pmcap_d1_support : 1;      /* [25] */
        u32 pmcap_d2_support : 1;      /* [26] */
        u32 pmcap_pme_support : 5;     /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pme_cap_header_u;

/* Define the union csr_pme_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pmcap_pwr_state : 2;     /* [1:0] */
        u32 pmcap_3reserved : 1;     /* [2] */
        u32 pmcap_no_soft_reset : 1; /* [3] */
        u32 pmcap_2reserved : 4;     /* [7:4] */
        u32 pmcap_pme_en : 1;        /* [8] */
        u32 pmcap_data_sel : 4;      /* [12:9] */
        u32 pmcap_data_scale : 2;    /* [14:13] */
        u32 pmcap_pme_status : 1;    /* [15] */
        u32 pmcap_1reserved : 6;     /* [21:16] */
        u32 pmcap_b2_b3_n : 1;       /* [22] */
        u32 pmcap_bpcc_en : 1;       /* [23] */
        u32 pmcap_data : 8;          /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pme_ctrl_status_u;

/* Define the union csr_acs_extended_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 acscap_id : 16;      /* [15:0] */
        u32 acscap_version : 4;  /* [19:16] */
        u32 acscap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_acs_extended_cap_header_u;

/* Define the union csr_acs_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 acscap_sv : 1;        /* [0] */
        u32 acscap_tb : 1;        /* [1] */
        u32 acscap_prr : 1;       /* [2] */
        u32 acscap_pcr : 1;       /* [3] */
        u32 acscap_uf : 1;        /* [4] */
        u32 acscap_pec : 1;       /* [5] */
        u32 acscap_dtp : 1;       /* [6] */
        u32 acscap_1reserved : 1; /* [7] */
        u32 acscap_ecvs : 8;      /* [15:8] */
        u32 acscap_sv_en : 1;     /* [16] */
        u32 acscap_tb_en : 1;     /* [17] */
        u32 acscap_prr_en : 1;    /* [18] */
        u32 acscap_pcr_en : 1;    /* [19] */
        u32 acscap_uf_en : 1;     /* [20] */
        u32 acscap_pec_en : 1;    /* [21] */
        u32 acscap_dtp_en : 1;    /* [22] */
        u32 acscap_0reserved : 9; /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_acs_ctrl_u;

/* Define the union csr_sriov_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_id : 16;      /* [15:0] */
        u32 sriovcap_version : 4;  /* [19:16] */
        u32 sriovcap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sriov_cap_header_u;

/* Define the union csr_sriov_cap_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_vf_mig_cap : 1;        /* [0] */
        u32 sriovcap_ari_cap_hier_pres : 1; /* [1] */
        u32 sriovcap_0reserved : 19;        /* [20:2] */
        u32 sriovcap_vf_mig_int : 11;       /* [31:21] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sriov_cap_u;

/* Define the union csr_sriov_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_vf_en : 1;         /* [0] */
        u32 sriovcap_vf_mig_en : 1;     /* [1] */
        u32 sriovcap_vf_mig_int_en : 1; /* [2] */
        u32 sriovcap_vf_mse : 1;        /* [3] */
        u32 sriovcap_ari_cap_hier : 1;  /* [4] */
        u32 sriovcap_2reserved : 11;    /* [15:5] */
        u32 sriovcap_vf_mig_status : 1; /* [16] */
        u32 sriovcap_1reserved : 15;    /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sriov_ctrl_u;

/* Define the union csr_init_vf_number_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_initial_vf : 16; /* [15:0] */
        u32 sriovcap_totl_vfs : 16;   /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_init_vf_number_u;

/* Define the union csr_func_dep_vf_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_num_of_vf : 16;      /* [15:0] */
        u32 sriovcap_func_depen_link : 8; /* [23:16] */
        u32 sriovcap_3reserved : 8;       /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_func_dep_vf_num_u;

/* Define the union csr_vf_rid_setting_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_vf_offset : 16; /* [15:0] */
        u32 sriovcap_vf_stride : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_rid_setting_u;

/* Define the union csr_vf_device_id_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_4reserved : 16;    /* [15:0] */
        u32 sriovcap_vf_device_id : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_device_id_u;

/* Define the union csr_vf_page_size_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_support_page_size : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_page_size_u;

/* Define the union csr_system_page_size_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_sys_page_size : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_system_page_size_u;

/* Define the union csr_vf_bar0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_5reserved : 2;           /* [1:0] */
        u32 sriovcap_vf_bar0_width : 1;       /* [2] */
        u32 sriovcap_vf_bar0_prefetch_en : 1; /* [3] */
        u32 sriovcap_resvd : 12;              /* [15:4] */
        u32 sriovcap_vf_bar0_addr : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_bar0_u;

/* Define the union csr_vf_bar1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_vf_bar1_addr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_bar1_u;

/* Define the union csr_vf_bar2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_7reserved : 2;           /* [1:0] */
        u32 sriovcap_vf_bar2_width : 1;       /* [2] */
        u32 sriovcap_vf_bar2_prefetch_en : 1; /* [3] */
        u32 sriovcap_resv : 16;               /* [19:4] */
        u32 sriovcap_vf_bar2_addr : 12;       /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_bar2_u;

/* Define the union csr_vf_bar3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_vf_bar3_addr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_bar3_u;

/* Define the union csr_vf_bar4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_9reserved : 2;           /* [1:0] */
        u32 sriovcap_vf_bar4_width : 1;       /* [2] */
        u32 sriovcap_vf_bar4_prefetch_en : 1; /* [3] */
        u32 sriovcap_vf_bar4_addr : 28;       /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_bar4_u;

/* Define the union csr_vf_bar5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_10reserved : 3;          /* [2:0] */
        u32 sriovcap_vf_bar5_prefetch_en : 1; /* [3] */
        u32 sriovcap_vf_bar5_addr : 28;       /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_bar5_u;

/* Define the union csr_vf_mig_state_array_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sriovcap_vf_mig_state_bir : 3;     /* [2:0] */
        u32 sriovcap_vf_mig_state_offset : 29; /* [31:3] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_mig_state_array_u;

/* Define the union csr_tph_extended_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tphcap_id : 16;      /* [15:0] */
        u32 tphcap_version : 4;  /* [19:16] */
        u32 tphcap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_tph_extended_cap_header_u;

/* Define the union csr_tph_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tphcap_nsms : 1;         /* [0] */
        u32 tphcap_ivms : 1;         /* [1] */
        u32 tphcap_sdms : 1;         /* [2] */
        u32 tphcap_resvdp0 : 5;      /* [7:3] */
        u32 tphcap_etrs : 1;         /* [8] */
        u32 tphcap_stl : 2;          /* [10:9] */
        u32 tphcap_resvdp1 : 5;      /* [15:11] */
        u32 tphcap_st_tbl_size : 11; /* [26:16] */
        u32 tphcap_resvdp2 : 5;      /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_tph_ctrl_u;

/* Define the union csr_tph_egress_ctrl0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tphcap_sms : 3;      /* [2:0] */
        u32 tphcap_resvdp3 : 5;  /* [7:3] */
        u32 tphcap_tre : 1;      /* [8] */
        u32 tphcap_resvdp4 : 23; /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_tph_egress_ctrl0_u;

/* Define the union csr_pasid_extended_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pasidcap_id : 16;      /* [15:0] */
        u32 pasidcap_version : 4;  /* [19:16] */
        u32 pasidcap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pasid_extended_cap_header_u;

/* Define the union csr_pasid_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pasidcap_resvp0 : 1;   /* [0] */
        u32 pasidcap_eps : 1;      /* [1] */
        u32 pasidcap_pms : 1;      /* [2] */
        u32 pasidcap_resvp1 : 5;   /* [7:3] */
        u32 pasidcap_mpw : 5;      /* [12:8] */
        u32 pasidcap_resvp2 : 3;   /* [15:13] */
        u32 pasidcap_pasid_en : 1; /* [16] */
        u32 pasidcap_epe : 1;      /* [17] */
        u32 pasidcap_pme : 1;      /* [18] */
        u32 pasidcap_resvp3 : 13;  /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pasid_ctrl_u;

/* Define the union csr_aer_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_id : 16;      /* [15:0] */
        u32 aercap_version : 4;  /* [19:16] */
        u32 aercap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_aer_cap_header_u;

/* Define the union csr_uncr_err_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_undefined_4 : 1;        /* [0] */
        u32 aercap_2reserved : 3;          /* [3:1] */
        u32 aercap_dl_protocal_err_st : 1; /* [4] */
        u32 aercap_sur_down_err_st : 1;    /* [5] */
        u32 aercap_1reserved : 6;          /* [11:6] */
        u32 aercap_poisoned_tlp_st : 1;    /* [12] */
        u32 aercap_fc_protocol_err_st : 1; /* [13] */
        u32 aercap_cpl_timeeout_st : 1;    /* [14] */
        u32 aercap_cpl_abort_st : 1;       /* [15] */
        u32 aercap_unexp_cpl_st : 1;       /* [16] */
        u32 aercap_rcv_overflow_st : 1;    /* [17] */
        u32 aercap_mal_tlp_st : 1;         /* [18] */
        u32 aercap_ecrc_err_st : 1;        /* [19] */
        u32 aercap_ur_err_st : 1;          /* [20] */
        u32 aercap_acs_vio_st : 1;         /* [21] */
        u32 aercap_ue_internal_st : 1;     /* [22] */
        u32 aercap_mc_blk_st : 1;          /* [23] */
        u32 aercap_atomicop_eg_blk_st : 1; /* [24] */
        u32 aercap_tlp_pfx_blk_err_st : 1; /* [25] */
        u32 aercap_0reserved : 6;          /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_uncr_err_status_u;

/* Define the union csr_uncr_err_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_undefined_8 : 1;          /* [0] */
        u32 aercap_5reserved : 3;            /* [3:1] */
        u32 aercap_dl_protocal_err_mask : 1; /* [4] */
        u32 aercap_sur_down_err_mask : 1;    /* [5] */
        u32 aercap_4reserved : 6;            /* [11:6] */
        u32 aercap_poisoned_tlp_mask : 1;    /* [12] */
        u32 aercap_fc_protocol_err_mask : 1; /* [13] */
        u32 aercap_cpl_timeeout_mask : 1;    /* [14] */
        u32 aercap_cpl_abort_mask : 1;       /* [15] */
        u32 aercap_unexp_cpl_mask : 1;       /* [16] */
        u32 aercap_rcv_overflow_mask : 1;    /* [17] */
        u32 aercap_mal_tlp_mask : 1;         /* [18] */
        u32 aercap_ecrc_err_mask : 1;        /* [19] */
        u32 aercap_ur_err_mask : 1;          /* [20] */
        u32 aercap_acs_vio_mask : 1;         /* [21] */
        u32 aercap_uncor_int_err_mask : 1;   /* [22] */
        u32 aercap_mc_blk_mask : 1;          /* [23] */
        u32 aercap_atomicop_eg_blk_mask : 1; /* [24] */
        u32 aercap_tlp_pfx_blk_err_mask : 1; /* [25] */
        u32 aercap_3reserved : 6;            /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_uncr_err_mask_u;

/* Define the union csr_uncr_err_severity_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_undefined_c : 1;         /* [0] */
        u32 aercap_8reserved : 3;           /* [3:1] */
        u32 aercap_dl_protocal_err_ser : 1; /* [4] */
        u32 aercap_sur_down_err_ser : 1;    /* [5] */
        u32 aercap_7reserved : 6;           /* [11:6] */
        u32 aercap_poisoned_tlp_ser : 1;    /* [12] */
        u32 aercap_fc_protocol_err_ser : 1; /* [13] */
        u32 aercap_cpl_timeeout_ser : 1;    /* [14] */
        u32 aercap_cpl_abort_ser : 1;       /* [15] */
        u32 aercap_unexp_cpl_ser : 1;       /* [16] */
        u32 aercap_rcv_overflow_ser : 1;    /* [17] */
        u32 aercap_mal_tlp_ser : 1;         /* [18] */
        u32 aercap_ecrc_err_ser : 1;        /* [19] */
        u32 aercap_ur_err_ser : 1;          /* [20] */
        u32 aercap_acs_vio_ser : 1;         /* [21] */
        u32 aercap_uncor_int_err_ser : 1;   /* [22] */
        u32 aercap_mc_blk_ser : 1;          /* [23] */
        u32 aercap_atomicop_eg_blk_ser : 1; /* [24] */
        u32 aercap_tlp_pfx_blk_err_ser : 1; /* [25] */
        u32 aercap_6reserved : 6;           /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_uncr_err_severity_u;

/* Define the union csr_cor_err_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_rx_err_st : 1;              /* [0] */
        u32 aercap_11reserved : 5;             /* [5:1] */
        u32 aercap_bad_tlp_st : 1;             /* [6] */
        u32 aercap_bad_dllp_st : 1;            /* [7] */
        u32 aercap_reply_num_rollover_st : 1;  /* [8] */
        u32 aercap_10reserved : 3;             /* [11:9] */
        u32 aercap_reply_timer_timout_st : 1;  /* [12] */
        u32 aercap_adv_non_fatal_err_st : 1;   /* [13] */
        u32 aercap_cor_int_err_st : 1;         /* [14] */
        u32 aercap_header_log_overflow_st : 1; /* [15] */
        u32 aercap_9reserved : 16;             /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cor_err_status_u;

/* Define the union csr_cor_err_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_rx_err_mask : 1;              /* [0] */
        u32 aercap_14reserved : 5;               /* [5:1] */
        u32 aercap_bad_tlp_mask : 1;             /* [6] */
        u32 aercap_bad_dllp_mask : 1;            /* [7] */
        u32 aercap_reply_num_rollover_mask : 1;  /* [8] */
        u32 aercap_13reserved : 3;               /* [11:9] */
        u32 aercap_reply_timer_timout_mask : 1;  /* [12] */
        u32 aercap_adv_non_fatal_err_mask : 1;   /* [13] */
        u32 aercap_cor_int_err_mask : 1;         /* [14] */
        u32 aercap_header_log_overflow_mask : 1; /* [15] */
        u32 aercap_12reserved : 16;              /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cor_err_mask_u;

/* Define the union csr_advacd_cap_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_first_err_ptr : 5;        /* [4:0] */
        u32 aercap_ecrc_gen_cap : 1;         /* [5] */
        u32 aercap_ecrc_gen_en : 1;          /* [6] */
        u32 aercap_ecrc_check_cap : 1;       /* [7] */
        u32 aercap_ecrc_check_en : 1;        /* [8] */
        u32 aercap_multi_hdr_rec_cap : 1;    /* [9] */
        u32 aercap_multi_hdr_rec_enable : 1; /* [10] */
        u32 aercap_tlp_prefix_lor_pre : 1;   /* [11] */
        u32 aercap_15reserved : 20;          /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_advacd_cap_ctrl_u;

/* Define the union csr_first_header_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_first_header_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_first_header_log_u;

/* Define the union csr_second_header_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_second_header_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_second_header_log_u;

/* Define the union csr_third_header_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_third_header_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_third_header_log_u;

/* Define the union csr_four_header_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_four_header_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_four_header_log_u;

/* Define the union csr_rwot_errwr_command_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_cor_err_en : 1;       /* [0] */
        u32 aercap_non_fatal_err_en : 1; /* [1] */
        u32 aercap_fatal_err_en : 1;     /* [2] */
        u32 aercap_16reserved : 29;      /* [31:3] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rwot_errwr_command_u;

/* Define the union csr_rwot_errwr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_core_err_rcv : 1;        /* [0] */
        u32 aercap_multi_cor_err_rcv : 1;   /* [1] */
        u32 aercap_uncor_err_rcv : 1;       /* [2] */
        u32 aercap_multi_uncor_err_rcv : 1; /* [3] */
        u32 aercap_first_uncor_err : 1;     /* [4] */
        u32 aercap_non_fatal_msg_rcv : 1;   /* [5] */
        u32 aercap_fatal_msg_rcv : 1;       /* [6] */
        u32 aercap_17reserved : 20;         /* [26:7] */
        u32 aercap_aer_int_number : 5;      /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rwot_errwr_status_u;

/* Define the union csr_err_source_iden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_err_cor_source : 16;     /* [15:0] */
        u32 aercap_err_non_cir_source : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_err_source_iden_u;

/* Define the union csr_first_prefix_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_first_prefix_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_first_prefix_log_u;

/* Define the union csr_second_prefix_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_second_prefix_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_second_prefix_log_u;

/* Define the union csr_third_prefix_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_third_prefix_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_third_prefix_log_u;

/* Define the union csr_four_prefix_log_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aercap_four_prefix_log : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_four_prefix_log_u;

/* Define the union csr_ari_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aricap_id : 16;      /* [15:0] */
        u32 aricap_version : 4;  /* [19:16] */
        u32 aricap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ari_cap_header_u;

/* Define the union csr_ari_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 aricap_mfvc_func_grp_cap : 1; /* [0] */
        u32 aricap_acs_func_grp_cap : 1;  /* [1] */
        u32 aricap_2reserved : 6;         /* [7:2] */
        u32 aricap_nxt_func_num : 8;      /* [15:8] */
        u32 aricap_mfvc_func_grp_en : 1;  /* [16] */
        u32 aricap_acs_func_grp_en : 1;   /* [17] */
        u32 aricap_1reserved : 2;         /* [19:18] */
        u32 aricap_func_group : 3;        /* [22:20] */
        u32 aricap_0reserved : 9;         /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ari_ctrl_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_pcihdr_id_u pcihdr_id;                                 /* 0 */
    volatile csr_pcihdr_cmdsts_u pcihdr_cmdsts;                         /* 4 */
    volatile csr_pcihdr_clsrev_u pcihdr_clsrev;                         /* 8 */
    volatile csr_pcihdr_misc_u pcihdr_misc;                             /* C */
    volatile csr_pcihdr_bar0_u pcihdr_bar0;                             /* 10 */
    volatile csr_pcihdr_bar1_u pcihdr_bar1;                             /* 14 */
    volatile csr_pcihdr_bar2_u pcihdr_bar2;                             /* 18 */
    volatile csr_pcihdr_bar3_u pcihdr_bar3;                             /* 1C */
    volatile csr_pcihdr_bar4_u pcihdr_bar4;                             /* 20 */
    volatile csr_pcihdr_bar5_u pcihdr_bar5;                             /* 24 */
    volatile csr_pcihdr_cbus_ptr_u pcihdr_cbus_ptr;                     /* 28 */
    volatile csr_pcihdr_subsys_u pcihdr_subsys;                         /* 2C */
    volatile csr_pcihdr_exprwm_u pcihdr_exprwm;                         /* 30 */
    volatile csr_pcihdr_capptr_u pcihdr_capptr;                         /* 34 */
    volatile csr_pci_rsvd_u pci_rsvd;                                   /* 38 */
    volatile csr_pcihdr_int_u pcihdr_int;                               /* 3C */
    volatile csr_pcie_capability_header_u pcie_capability_header;       /* 40 */
    volatile csr_device_capbility_u device_capbility;                   /* 44 */
    volatile csr_device_ctrl_status_u device_ctrl_status;               /* 48 */
    volatile csr_link_capbility_u link_capbility;                       /* 4C */
    volatile csr_link_ctrl_status_u link_ctrl_status;                   /* 50 */
    volatile csr_slot_capability_u slot_capability;                     /* 54 */
    volatile csr_slot_ctrl_status_u slot_ctrl_status;                   /* 58 */
    volatile csr_root_ctrl_status_u root_ctrl_status;                   /* 5C */
    volatile csr_root_status_u root_status;                             /* 60 */
    volatile csr_device_capability2_u device_capability2;               /* 64 */
    volatile csr_device_ctrl2_u device_ctrl2;                           /* 68 */
    volatile csr_link_capability2_u link_capability2;                   /* 6C */
    volatile csr_link_ctrl_status2_u link_ctrl_status2;                 /* 70 */
    volatile csr_slot_cap_2_u slot_cap_2;                               /* 74 */
    volatile csr_slot_ctrl_2_u slot_ctrl_2;                             /* 78 */
    volatile csr_msi_cap_header_u msi_cap_header;                       /* 80 */
    volatile csr_msi_addr_u msi_addr;                                   /* 84 */
    volatile csr_msi_up_addr_u msi_up_addr;                             /* 88 */
    volatile csr_msi_data_u msi_data;                                   /* 8C */
    volatile csr_msi_mask_u msi_mask;                                   /* 90 */
    volatile csr_msi_pending_u msi_pending;                             /* 94 */
    volatile csr_msix_cap_header_u msix_cap_header;                     /* A0 */
    volatile csr_msix_table_u msix_table;                               /* A4 */
    volatile csr_msix_pba_u msix_pba;                                   /* A8 */
    volatile csr_pme_cap_header_u pme_cap_header;                       /* B0 */
    volatile csr_pme_ctrl_status_u pme_ctrl_status;                     /* B4 */
    volatile csr_acs_extended_cap_header_u acs_extended_cap_header;     /* 100 */
    volatile csr_acs_ctrl_u acs_ctrl;                                   /* 104 */
    volatile csr_sriov_cap_header_u sriov_cap_header;                   /* 200 */
    volatile csr_sriov_cap_u sriov_cap;                                 /* 204 */
    volatile csr_sriov_ctrl_u sriov_ctrl;                               /* 208 */
    volatile csr_init_vf_number_u init_vf_number;                       /* 20C */
    volatile csr_func_dep_vf_num_u func_dep_vf_num;                     /* 210 */
    volatile csr_vf_rid_setting_u vf_rid_setting;                       /* 214 */
    volatile csr_vf_device_id_u vf_device_id;                           /* 218 */
    volatile csr_vf_page_size_u vf_page_size;                           /* 21C */
    volatile csr_system_page_size_u system_page_size;                   /* 220 */
    volatile csr_vf_bar0_u vf_bar0;                                     /* 224 */
    volatile csr_vf_bar1_u vf_bar1;                                     /* 228 */
    volatile csr_vf_bar2_u vf_bar2;                                     /* 22C */
    volatile csr_vf_bar3_u vf_bar3;                                     /* 230 */
    volatile csr_vf_bar4_u vf_bar4;                                     /* 234 */
    volatile csr_vf_bar5_u vf_bar5;                                     /* 238 */
    volatile csr_vf_mig_state_array_u vf_mig_state_array;               /* 23C */
    volatile csr_tph_extended_cap_header_u tph_extended_cap_header;     /* 300 */
    volatile csr_tph_ctrl_u tph_ctrl;                                   /* 304 */
    volatile csr_tph_egress_ctrl0_u tph_egress_ctrl0;                   /* 308 */
    volatile csr_pasid_extended_cap_header_u pasid_extended_cap_header; /* 320 */
    volatile csr_pasid_ctrl_u pasid_ctrl;                               /* 324 */
    volatile csr_aer_cap_header_u aer_cap_header;                       /* 400 */
    volatile csr_uncr_err_status_u uncr_err_status;                     /* 404 */
    volatile csr_uncr_err_mask_u uncr_err_mask;                         /* 408 */
    volatile csr_uncr_err_severity_u uncr_err_severity;                 /* 40C */
    volatile csr_cor_err_status_u cor_err_status;                       /* 410 */
    volatile csr_cor_err_mask_u cor_err_mask;                           /* 414 */
    volatile csr_advacd_cap_ctrl_u advacd_cap_ctrl;                     /* 418 */
    volatile csr_first_header_log_u first_header_log;                   /* 41C */
    volatile csr_second_header_log_u second_header_log;                 /* 420 */
    volatile csr_third_header_log_u third_header_log;                   /* 424 */
    volatile csr_four_header_log_u four_header_log;                     /* 428 */
    volatile csr_rwot_errwr_command_u rwot_errwr_command;               /* 42C */
    volatile csr_rwot_errwr_status_u rwot_errwr_status;                 /* 430 */
    volatile csr_err_source_iden_u err_source_iden;                     /* 434 */
    volatile csr_first_prefix_log_u first_prefix_log;                   /* 438 */
    volatile csr_second_prefix_log_u second_prefix_log;                 /* 43C */
    volatile csr_third_prefix_log_u third_prefix_log;                   /* 440 */
    volatile csr_four_prefix_log_u four_prefix_log;                     /* 444 */
    volatile csr_ari_cap_header_u ari_cap_header;                       /* 450 */
    volatile csr_ari_ctrl_u ari_ctrl;                                   /* 454 */
} S_peh_pf_regs_REGS_TYPE;

/* Declare the struct pointor of the module peh_pf_regs */
extern volatile S_peh_pf_regs_REGS_TYPE *goppeh_pf_regsAllReg;

/* Declare the functions that set the member value */
int iSetPCIHDR_ID_hdr_vendor_id(unsigned int uhdr_vendor_id);
int iSetPCIHDR_ID_hdr_device_id(unsigned int uhdr_device_id);
int iSetPCIHDR_CMDSTS_hdr_io_space_en(unsigned int uhdr_io_space_en);
int iSetPCIHDR_CMDSTS_hdr_mem_space_en(unsigned int uhdr_mem_space_en);
int iSetPCIHDR_CMDSTS_hdr_bus_master_en(unsigned int uhdr_bus_master_en);
int iSetPCIHDR_CMDSTS_hdr_special_cycle_en(unsigned int uhdr_special_cycle_en);
int iSetPCIHDR_CMDSTS_hdr_mem_wr_invld_en(unsigned int uhdr_mem_wr_invld_en);
int iSetPCIHDR_CMDSTS_hdr_vga_snoop_en(unsigned int uhdr_vga_snoop_en);
int iSetPCIHDR_CMDSTS_hdr_parity_err_resp(unsigned int uhdr_parity_err_resp);
int iSetPCIHDR_CMDSTS_hdr_idsel_stepping(unsigned int uhdr_idsel_stepping);
int iSetPCIHDR_CMDSTS_hdr_serr_en(unsigned int uhdr_serr_en);
int iSetPCIHDR_CMDSTS_hdr_fast_b2b_en(unsigned int uhdr_fast_b2b_en);
int iSetPCIHDR_CMDSTS_hdr_intx_disable(unsigned int uhdr_intx_disable);
int iSetPCIHDR_CMDSTS_hdr_rved(unsigned int uhdr_rved);
int iSetPCIHDR_CMDSTS_hdr_intx_status(unsigned int uhdr_intx_status);
int iSetPCIHDR_CMDSTS_hdr_cap_list(unsigned int uhdr_cap_list);
int iSetPCIHDR_CMDSTS_hdr_66mhz_cap(unsigned int uhdr_66mhz_cap);
int iSetPCIHDR_CMDSTS_hdr_0reserved(unsigned int uhdr_0reserved);
int iSetPCIHDR_CMDSTS_hdr_fastb2b_cap(unsigned int uhdr_fastb2b_cap);
int iSetPCIHDR_CMDSTS_hdr_mdata_par_err(unsigned int uhdr_mdata_par_err);
int iSetPCIHDR_CMDSTS_hdr_devsel_timing(unsigned int uhdr_devsel_timing);
int iSetPCIHDR_CMDSTS_hdr_sig_target_abort(unsigned int uhdr_sig_target_abort);
int iSetPCIHDR_CMDSTS_hdr_rx_target_abort(unsigned int uhdr_rx_target_abort);
int iSetPCIHDR_CMDSTS_hdr_rx_master_abort(unsigned int uhdr_rx_master_abort);
int iSetPCIHDR_CMDSTS_hdr_rx_sys_err(unsigned int uhdr_rx_sys_err);
int iSetPCIHDR_CMDSTS_hdr_deteted_par_err(unsigned int uhdr_deteted_par_err);
int iSetPCIHDR_CLSREV_hdr_revision_id(unsigned int uhdr_revision_id);
int iSetPCIHDR_CLSREV_hdr_program_inf(unsigned int uhdr_program_inf);
int iSetPCIHDR_CLSREV_hdr_sub_class_code(unsigned int uhdr_sub_class_code);
int iSetPCIHDR_CLSREV_hdr_base_class_code(unsigned int uhdr_base_class_code);
int iSetPCIHDR_MISC_hdr_cachlie_size(unsigned int uhdr_cachlie_size);
int iSetPCIHDR_MISC_hdr_latency_timer(unsigned int uhdr_latency_timer);
int iSetPCIHDR_MISC_hdr_header_type(unsigned int uhdr_header_type);
int iSetPCIHDR_MISC_hdr_multfunc_dev(unsigned int uhdr_multfunc_dev);
int iSetPCIHDR_MISC_hdr_bist_result(unsigned int uhdr_bist_result);
int iSetPCIHDR_MISC_hdr_1reserved(unsigned int uhdr_1reserved);
int iSetPCIHDR_MISC_hdr_start_bist(unsigned int uhdr_start_bist);
int iSetPCIHDR_MISC_hdr_bist_cap(unsigned int uhdr_bist_cap);
int iSetPCIHDR_BAR0_hdr_bar0_type(unsigned int uhdr_bar0_type);
int iSetPCIHDR_BAR0_hdr_bar0_reserved(unsigned int uhdr_bar0_reserved);
int iSetPCIHDR_BAR0_hdr_bar0_width(unsigned int uhdr_bar0_width);
int iSetPCIHDR_BAR0_hdr_bar0_prefetch_en(unsigned int uhdr_bar0_prefetch_en);
int iSetPCIHDR_BAR0_hdr_2reserved(unsigned int uhdr_2reserved);
int iSetPCIHDR_BAR0_hdr_bar0_addr(unsigned int uhdr_bar0_addr);
int iSetPCIHDR_BAR1_hdr_bar1_type(unsigned int uhdr_bar1_type);
int iSetPCIHDR_BAR1_hdr_bar1_reserved(unsigned int uhdr_bar1_reserved);
int iSetPCIHDR_BAR1_hdr_bar1_width(unsigned int uhdr_bar1_width);
int iSetPCIHDR_BAR1_hdr_bar1_prefetch_en(unsigned int uhdr_bar1_prefetch_en);
int iSetPCIHDR_BAR1_hdr_bar1_2reserved(unsigned int uhdr_bar1_2reserved);
int iSetPCIHDR_BAR1_hdr_bar1_addr(unsigned int uhdr_bar1_addr);
int iSetPCIHDR_BAR2_hdr_bar2_type(unsigned int uhdr_bar2_type);
int iSetPCIHDR_BAR2_hdr_bar2_reserved(unsigned int uhdr_bar2_reserved);
int iSetPCIHDR_BAR2_hdr_bar2_width(unsigned int uhdr_bar2_width);
int iSetPCIHDR_BAR2_hdr_bar2_prefetch_en(unsigned int uhdr_bar2_prefetch_en);
int iSetPCIHDR_BAR2_hdr_bar2_2reserved(unsigned int uhdr_bar2_2reserved);
int iSetPCIHDR_BAR2_hdr_bar2_addr(unsigned int uhdr_bar2_addr);
int iSetPCIHDR_BAR3_hdr_bar3_type(unsigned int uhdr_bar3_type);
int iSetPCIHDR_BAR3_hdr_bar3_reserved(unsigned int uhdr_bar3_reserved);
int iSetPCIHDR_BAR3_hdr_bar3_width(unsigned int uhdr_bar3_width);
int iSetPCIHDR_BAR3_hdr_bar3_prefetch_en(unsigned int uhdr_bar3_prefetch_en);
int iSetPCIHDR_BAR3_hdr_bar3_2reserved(unsigned int uhdr_bar3_2reserved);
int iSetPCIHDR_BAR3_hdr_bar3_addr(unsigned int uhdr_bar3_addr);
int iSetPCIHDR_BAR4_hdr_bar4_type(unsigned int uhdr_bar4_type);
int iSetPCIHDR_BAR4_hdr_bar4_reserved(unsigned int uhdr_bar4_reserved);
int iSetPCIHDR_BAR4_hdr_bar4_width(unsigned int uhdr_bar4_width);
int iSetPCIHDR_BAR4_hdr_bar4_prefetch_en(unsigned int uhdr_bar4_prefetch_en);
int iSetPCIHDR_BAR4_hdr_bar4_2reserved(unsigned int uhdr_bar4_2reserved);
int iSetPCIHDR_BAR4_hdr_bar4_addr(unsigned int uhdr_bar4_addr);
int iSetPCIHDR_BAR5_hdr_bar5_addr(unsigned int uhdr_bar5_addr);
int iSetPCIHDR_CBUS_PTR_hdr_carbus_cis_ptr(unsigned int uhdr_carbus_cis_ptr);
int iSetPCIHDR_SUBSYS_hdr_sys_vendor_id(unsigned int uhdr_sys_vendor_id);
int iSetPCIHDR_SUBSYS_hdr_sub_sys_id(unsigned int uhdr_sub_sys_id);
int iSetPCIHDR_EXPRWM_hdr_ext_rom_enable(unsigned int uhdr_ext_rom_enable);
int iSetPCIHDR_EXPRWM_hdr_6reserved(unsigned int uhdr_6reserved);
int iSetPCIHDR_EXPRWM_hdr_ext_rom_base_addr(unsigned int uhdr_ext_rom_base_addr);
int iSetPCIHDR_CAPPTR_hdr_cap_ptr(unsigned int uhdr_cap_ptr);
int iSetPCIHDR_CAPPTR_hdr_7reserved(unsigned int uhdr_7reserved);
int iSetPCI_RSVD_hdr_8reserved(unsigned int uhdr_8reserved);
int iSetPCIHDR_INT_hdr_int_line(unsigned int uhdr_int_line);
int iSetPCIHDR_INT_hdr_int_pin(unsigned int uhdr_int_pin);
int iSetPCIHDR_INT_hdr_3creserved(unsigned int uhdr_3creserved);
int iSetPCIE_CAPABILITY_HEADER_pcap_pci_capid(unsigned int upcap_pci_capid);
int iSetPCIE_CAPABILITY_HEADER_pcap_nxt_ptr(unsigned int upcap_nxt_ptr);
int iSetPCIE_CAPABILITY_HEADER_pcap_pci_cap_ver(unsigned int upcap_pci_cap_ver);
int iSetPCIE_CAPABILITY_HEADER_pcap_port_type(unsigned int upcap_port_type);
int iSetPCIE_CAPABILITY_HEADER_pcap_slot_implement(unsigned int upcap_slot_implement);
int iSetPCIE_CAPABILITY_HEADER_pcap_int_msg_num(unsigned int upcap_int_msg_num);
int iSetPCIE_CAPABILITY_HEADER_pcap_15reserved(unsigned int upcap_15reserved);
int iSetDEVICE_CAPBILITY_pcap_max_payload_size_support(unsigned int upcap_max_payload_size_support);
int iSetDEVICE_CAPBILITY_pcap_phanotom_fun_sup(unsigned int upcap_phanotom_fun_sup);
int iSetDEVICE_CAPBILITY_pcap_ext_tag_sup(unsigned int upcap_ext_tag_sup);
int iSetDEVICE_CAPBILITY_pcap_ep_l0s_accept_lat(unsigned int upcap_ep_l0s_accept_lat);
int iSetDEVICE_CAPBILITY_pcap_ep_l1_accept_lat(unsigned int upcap_ep_l1_accept_lat);
int iSetDEVICE_CAPBILITY_pcap_undefine_04(unsigned int upcap_undefine_04);
int iSetDEVICE_CAPBILITY_pcap_ro_base_err_rpt(unsigned int upcap_ro_base_err_rpt);
int iSetDEVICE_CAPBILITY_pcap_0reserved(unsigned int upcap_0reserved);
int iSetDEVICE_CAPBILITY_pcap_cap_slot_pwr_limit_val(unsigned int upcap_cap_slot_pwr_limit_val);
int iSetDEVICE_CAPBILITY_pcap_cap_slot_pwr_sca(unsigned int upcap_cap_slot_pwr_sca);
int iSetDEVICE_CAPBILITY_pcap_flr_cap(unsigned int upcap_flr_cap);
int iSetDEVICE_CAPBILITY_pcap_16reserved(unsigned int upcap_16reserved);
int iSetDEVICE_CTRL_STATUS_pcap_cor_err_rpt_en(unsigned int upcap_cor_err_rpt_en);
int iSetDEVICE_CTRL_STATUS_pcap_non_fat_rpt_en(unsigned int upcap_non_fat_rpt_en);
int iSetDEVICE_CTRL_STATUS_pcap_fat_err_rpt_en(unsigned int upcap_fat_err_rpt_en);
int iSetDEVICE_CTRL_STATUS_pcap_ur_rpt_en(unsigned int upcap_ur_rpt_en);
int iSetDEVICE_CTRL_STATUS_pcap_relax_order_en(unsigned int upcap_relax_order_en);
int iSetDEVICE_CTRL_STATUS_pcap_max_payload_size(unsigned int upcap_max_payload_size);
int iSetDEVICE_CTRL_STATUS_pcap_extend_tag_en(unsigned int upcap_extend_tag_en);
int iSetDEVICE_CTRL_STATUS_pcap_phatom_func_en(unsigned int upcap_phatom_func_en);
int iSetDEVICE_CTRL_STATUS_pcap_aux_pwr_pm_en(unsigned int upcap_aux_pwr_pm_en);
int iSetDEVICE_CTRL_STATUS_pcap_no_snoop_en(unsigned int upcap_no_snoop_en);
int iSetDEVICE_CTRL_STATUS_pcap_max_read_req_size(unsigned int upcap_max_read_req_size);
int iSetDEVICE_CTRL_STATUS_pcap_init_flr_reset_rwwo(unsigned int upcap_init_flr_reset_rwwo);
int iSetDEVICE_CTRL_STATUS_pcap_cor_err_detect(unsigned int upcap_cor_err_detect);
int iSetDEVICE_CTRL_STATUS_pcap_non_fata_detect(unsigned int upcap_non_fata_detect);
int iSetDEVICE_CTRL_STATUS_pcap_fat_err_detect(unsigned int upcap_fat_err_detect);
int iSetDEVICE_CTRL_STATUS_pcap_ur_detect(unsigned int upcap_ur_detect);
int iSetDEVICE_CTRL_STATUS_pcap_aux_pwr_detect(unsigned int upcap_aux_pwr_detect);
int iSetDEVICE_CTRL_STATUS_pcap_tlp_pending(unsigned int upcap_tlp_pending);
int iSetDEVICE_CTRL_STATUS_pcap_1reserved(unsigned int upcap_1reserved);
int iSetLINK_CAPBILITY_pcap_max_link_speed(unsigned int upcap_max_link_speed);
int iSetLINK_CAPBILITY_pcap_max_link_width(unsigned int upcap_max_link_width);
int iSetLINK_CAPBILITY_pcap_aspm_sup(unsigned int upcap_aspm_sup);
int iSetLINK_CAPBILITY_pcap_l0_exit_lat(unsigned int upcap_l0_exit_lat);
int iSetLINK_CAPBILITY_pcap_l1_exit_lat(unsigned int upcap_l1_exit_lat);
int iSetLINK_CAPBILITY_pcap_clock_pm(unsigned int upcap_clock_pm);
int iSetLINK_CAPBILITY_pcap_surprise_dn_err_rpt_cap(unsigned int upcap_surprise_dn_err_rpt_cap);
int iSetLINK_CAPBILITY_pcap_dl_link_act_rpt_cap(unsigned int upcap_dl_link_act_rpt_cap);
int iSetLINK_CAPBILITY_pcap_link_band_notice_cap(unsigned int upcap_link_band_notice_cap);
int iSetLINK_CAPBILITY_pcap_aspm_opt_compliance(unsigned int upcap_aspm_opt_compliance);
int iSetLINK_CAPBILITY_pcap_1reserved(unsigned int upcap_1reserved);
int iSetLINK_CAPBILITY_pcap_port_num(unsigned int upcap_port_num);
int iSetLINK_CTRL_STATUS_pcap_aspm_ctrl(unsigned int upcap_aspm_ctrl);
int iSetLINK_CTRL_STATUS_pcap_4reserved(unsigned int upcap_4reserved);
int iSetLINK_CTRL_STATUS_pcap_rcb(unsigned int upcap_rcb);
int iSetLINK_CTRL_STATUS_pcap_link_disable(unsigned int upcap_link_disable);
int iSetLINK_CTRL_STATUS_pcap_retrain_link(unsigned int upcap_retrain_link);
int iSetLINK_CTRL_STATUS_pcap_common_clk_cfg(unsigned int upcap_common_clk_cfg);
int iSetLINK_CTRL_STATUS_pcap_extended_sync(unsigned int upcap_extended_sync);
int iSetLINK_CTRL_STATUS_pcap_clock_pm_en(unsigned int upcap_clock_pm_en);
int iSetLINK_CTRL_STATUS_pcap_hw_auto_width_dis(unsigned int upcap_hw_auto_width_dis);
int iSetLINK_CTRL_STATUS_pcap_link_band_int_en(unsigned int upcap_link_band_int_en);
int iSetLINK_CTRL_STATUS_pcap_link_auto_band_int_en(unsigned int upcap_link_auto_band_int_en);
int iSetLINK_CTRL_STATUS_pcap_3reserved(unsigned int upcap_3reserved);
int iSetLINK_CTRL_STATUS_pcap_mac_cur_link_spped(unsigned int upcap_mac_cur_link_spped);
int iSetLINK_CTRL_STATUS_pcap_mac_cur_link_width(unsigned int upcap_mac_cur_link_width);
int iSetLINK_CTRL_STATUS_pcap_undefined_12(unsigned int upcap_undefined_12);
int iSetLINK_CTRL_STATUS_pcap_link_training(unsigned int upcap_link_training);
int iSetLINK_CTRL_STATUS_pcap_slot_clk_cfg(unsigned int upcap_slot_clk_cfg);
int iSetLINK_CTRL_STATUS_pcap_dl_cfg_link_active(unsigned int upcap_dl_cfg_link_active);
int iSetLINK_CTRL_STATUS_pcap_link_band_status(unsigned int upcap_link_band_status);
int iSetLINK_CTRL_STATUS_pcap_link_auto_band_status(unsigned int upcap_link_auto_band_status);
int iSetSLOT_CAPABILITY_pcap_att_button_pre(unsigned int upcap_att_button_pre);
int iSetSLOT_CAPABILITY_pcap_pwr_ctrl_pre(unsigned int upcap_pwr_ctrl_pre);
int iSetSLOT_CAPABILITY_pcap_msl_sensor_pre(unsigned int upcap_msl_sensor_pre);
int iSetSLOT_CAPABILITY_pcap_att_indecator_pre(unsigned int upcap_att_indecator_pre);
int iSetSLOT_CAPABILITY_pcap_pwr_indicator_pre(unsigned int upcap_pwr_indicator_pre);
int iSetSLOT_CAPABILITY_pcap_hot_plug_surprise(unsigned int upcap_hot_plug_surprise);
int iSetSLOT_CAPABILITY_pcap_hot_plug_cap(unsigned int upcap_hot_plug_cap);
int iSetSLOT_CAPABILITY_pcap_slot_pwr_limit_val(unsigned int upcap_slot_pwr_limit_val);
int iSetSLOT_CAPABILITY_pcap_slot_pwr_limit_scale(unsigned int upcap_slot_pwr_limit_scale);
int iSetSLOT_CAPABILITY_pcap_elec_interlock_pre(unsigned int upcap_elec_interlock_pre);
int iSetSLOT_CAPABILITY_pcap_no_comman_cpled_sup(unsigned int upcap_no_comman_cpled_sup);
int iSetSLOT_CAPABILITY_pcap_physical_slot_num(unsigned int upcap_physical_slot_num);
int iSetSLOT_CTRL_STATUS_pcap_att_buttom_pre_en(unsigned int upcap_att_buttom_pre_en);
int iSetSLOT_CTRL_STATUS_pcap_pwr_fault_det_en(unsigned int upcap_pwr_fault_det_en);
int iSetSLOT_CTRL_STATUS_pcap_mrl_sensor_change_en(unsigned int upcap_mrl_sensor_change_en);
int iSetSLOT_CTRL_STATUS_pcap_presence_det_change_en(unsigned int upcap_presence_det_change_en);
int iSetSLOT_CTRL_STATUS_pcap_command_cpled_int_en(unsigned int upcap_command_cpled_int_en);
int iSetSLOT_CTRL_STATUS_pcap_hot_plug_int_en(unsigned int upcap_hot_plug_int_en);
int iSetSLOT_CTRL_STATUS_pcap_att_indicator_ctrl(unsigned int upcap_att_indicator_ctrl);
int iSetSLOT_CTRL_STATUS_pcap_pwr_indicator_ctrl(unsigned int upcap_pwr_indicator_ctrl);
int iSetSLOT_CTRL_STATUS_pcap_pwr_ctrled_ctrl(unsigned int upcap_pwr_ctrled_ctrl);
int iSetSLOT_CTRL_STATUS_pcap_elec_interlock_ctrl(unsigned int upcap_elec_interlock_ctrl);
int iSetSLOT_CTRL_STATUS_pcap_dl_state_change_en(unsigned int upcap_dl_state_change_en);
int iSetSLOT_CTRL_STATUS_pcap_6reserved(unsigned int upcap_6reserved);
int iSetSLOT_CTRL_STATUS_pcap_attention_button(unsigned int upcap_attention_button);
int iSetSLOT_CTRL_STATUS_pcap_pwr_fault_det(unsigned int upcap_pwr_fault_det);
int iSetSLOT_CTRL_STATUS_pcap_mrl_sensor_change(unsigned int upcap_mrl_sensor_change);
int iSetSLOT_CTRL_STATUS_pcap_presencd_det_change(unsigned int upcap_presencd_det_change);
int iSetSLOT_CTRL_STATUS_pcap_command_cpled(unsigned int upcap_command_cpled);
int iSetSLOT_CTRL_STATUS_pcap_mrl_sensor_st(unsigned int upcap_mrl_sensor_st);
int iSetSLOT_CTRL_STATUS_pcap_presencd_det_st(unsigned int upcap_presencd_det_st);
int iSetSLOT_CTRL_STATUS_pcap_elec_interlock_st(unsigned int upcap_elec_interlock_st);
int iSetSLOT_CTRL_STATUS_pcap_dl_state_change(unsigned int upcap_dl_state_change);
int iSetSLOT_CTRL_STATUS_pcap_5reserved(unsigned int upcap_5reserved);
int iSetROOT_CTRL_STATUS_pcap_7reserved(unsigned int upcap_7reserved);
int iSetROOT_STATUS_pcap_pme_rid(unsigned int upcap_pme_rid);
int iSetROOT_STATUS_pcap_pme_status(unsigned int upcap_pme_status);
int iSetROOT_STATUS_pcap_pme_pending(unsigned int upcap_pme_pending);
int iSetROOT_STATUS_pcap_8reserved(unsigned int upcap_8reserved);
int iSetDEVICE_CAPABILITY2_pcap_cpl_timeout_range(unsigned int upcap_cpl_timeout_range);
int iSetDEVICE_CAPABILITY2_pcap_cpl_timeout_disable_sup(unsigned int upcap_cpl_timeout_disable_sup);
int iSetDEVICE_CAPABILITY2_pcap_ari_fwd_sup(unsigned int upcap_ari_fwd_sup);
int iSetDEVICE_CAPABILITY2_pcap_atomicop_route_sup(unsigned int upcap_atomicop_route_sup);
int iSetDEVICE_CAPABILITY2_pcap_atomic_32bit_cpl_sup(unsigned int upcap_atomic_32bit_cpl_sup);
int iSetDEVICE_CAPABILITY2_pcap_atomic_64bit_cpl_sup(unsigned int upcap_atomic_64bit_cpl_sup);
int iSetDEVICE_CAPABILITY2_pcap_cas_128bit_cpl_sup(unsigned int upcap_cas_128bit_cpl_sup);
int iSetDEVICE_CAPABILITY2_pcap_no_roen_prpr_pass(unsigned int upcap_no_roen_prpr_pass);
int iSetDEVICE_CAPABILITY2_pcap_ltr_mech_sup(unsigned int upcap_ltr_mech_sup);
int iSetDEVICE_CAPABILITY2_pcap_tph_cpl_sup(unsigned int upcap_tph_cpl_sup);
int iSetDEVICE_CAPABILITY2_pcap_ln_sys_cls(unsigned int upcap_ln_sys_cls);
int iSetDEVICE_CAPABILITY2_pcap_sup_10bit_cpl_tag(unsigned int upcap_sup_10bit_cpl_tag);
int iSetDEVICE_CAPABILITY2_pcap_sup_10bit_req_tag(unsigned int upcap_sup_10bit_req_tag);
int iSetDEVICE_CAPABILITY2_pcap_obff_sup(unsigned int upcap_obff_sup);
int iSetDEVICE_CAPABILITY2_pcap_ext_fmt_sup(unsigned int upcap_ext_fmt_sup);
int iSetDEVICE_CAPABILITY2_pcap_end_end_pfx_sup(unsigned int upcap_end_end_pfx_sup);
int iSetDEVICE_CAPABILITY2_pcap_max_end_end_pfx(unsigned int upcap_max_end_end_pfx);
int iSetDEVICE_CAPABILITY2_pcap_9reserved(unsigned int upcap_9reserved);
int iSetDEVICE_CAPABILITY2_pcap_frs_sup(unsigned int upcap_frs_sup);
int iSetDEVICE_CTRL2_pcap_cpl_timeout_value(unsigned int upcap_cpl_timeout_value);
int iSetDEVICE_CTRL2_pcap_cpl_timeout_dis(unsigned int upcap_cpl_timeout_dis);
int iSetDEVICE_CTRL2_pcap_ari_fwd_en(unsigned int upcap_ari_fwd_en);
int iSetDEVICE_CTRL2_pcap_atomicop_req_en(unsigned int upcap_atomicop_req_en);
int iSetDEVICE_CTRL2_pcap_atomicop_egress_blk(unsigned int upcap_atomicop_egress_blk);
int iSetDEVICE_CTRL2_pcap_ido_req_en(unsigned int upcap_ido_req_en);
int iSetDEVICE_CTRL2_pcap_ido_cpl_en(unsigned int upcap_ido_cpl_en);
int iSetDEVICE_CTRL2_pcap_ltr_mech_en(unsigned int upcap_ltr_mech_en);
int iSetDEVICE_CTRL2_pcap_en_10bit_req_tag(unsigned int upcap_en_10bit_req_tag);
int iSetDEVICE_CTRL2_pcap_11reserved(unsigned int upcap_11reserved);
int iSetDEVICE_CTRL2_pcap_obff_en(unsigned int upcap_obff_en);
int iSetDEVICE_CTRL2_pcap_end_end_pfx_blk(unsigned int upcap_end_end_pfx_blk);
int iSetDEVICE_CTRL2_pcap_10reserved(unsigned int upcap_10reserved);
int iSetLINK_CAPABILITY2_pcap_13reserved(unsigned int upcap_13reserved);
int iSetLINK_CAPABILITY2_pcap_link_speed_sup(unsigned int upcap_link_speed_sup);
int iSetLINK_CAPABILITY2_pcap_cross_link_sup(unsigned int upcap_cross_link_sup);
int iSetLINK_CAPABILITY2_pcap_cfg_tx_lower_skp_cap(unsigned int upcap_cfg_tx_lower_skp_cap);
int iSetLINK_CAPABILITY2_pcap_cfg_rx_lower_skp_cap(unsigned int upcap_cfg_rx_lower_skp_cap);
int iSetLINK_CAPABILITY2_pcap_retimer_presence_detect(unsigned int upcap_retimer_presence_detect);
int iSetLINK_CAPABILITY2_pcap_retimer2_presence_detect(unsigned int upcap_retimer2_presence_detect);
int iSetLINK_CAPABILITY2_pcap_12reserved(unsigned int upcap_12reserved);
int iSetLINK_CAPABILITY2_pcap_drs_sup(unsigned int upcap_drs_sup);
int iSetLINK_CTRL_STATUS2_pcap_target_link_speed(unsigned int upcap_target_link_speed);
int iSetLINK_CTRL_STATUS2_pcap_enter_compliance(unsigned int upcap_enter_compliance);
int iSetLINK_CTRL_STATUS2_pcap_hw_auto_speed_dis(unsigned int upcap_hw_auto_speed_dis);
int iSetLINK_CTRL_STATUS2_pcap_selectable_de_emphasis(unsigned int upcap_selectable_de_emphasis);
int iSetLINK_CTRL_STATUS2_pcap_transmit_margin(unsigned int upcap_transmit_margin);
int iSetLINK_CTRL_STATUS2_pcap_enter_mod_compliance(unsigned int upcap_enter_mod_compliance);
int iSetLINK_CTRL_STATUS2_pcap_compliance_sos(unsigned int upcap_compliance_sos);
int iSetLINK_CTRL_STATUS2_pcap_compliance_preset_deemp(unsigned int upcap_compliance_preset_deemp);
int iSetLINK_CTRL_STATUS2_pcap_cur_deemp_level(unsigned int upcap_cur_deemp_level);
int iSetLINK_CTRL_STATUS2_pcap_eq_8g_complete(unsigned int upcap_eq_8g_complete);
int iSetLINK_CTRL_STATUS2_pcap_eq_8g_phase1_success(unsigned int upcap_eq_8g_phase1_success);
int iSetLINK_CTRL_STATUS2_pcap_eq_8g_phase2_success(unsigned int upcap_eq_8g_phase2_success);
int iSetLINK_CTRL_STATUS2_pcap_eq_8g_phase3_success(unsigned int upcap_eq_8g_phase3_success);
int iSetLINK_CTRL_STATUS2_pcap_link_8g_eq_req(unsigned int upcap_link_8g_eq_req);
int iSetLINK_CTRL_STATUS2_pcap_retimer_presence_detect(unsigned int upcap_retimer_presence_detect);
int iSetLINK_CTRL_STATUS2_pcap_retimer2_presence_detect(unsigned int upcap_retimer2_presence_detect);
int iSetLINK_CTRL_STATUS2_pcap_14reserved(unsigned int upcap_14reserved);
int iSetLINK_CTRL_STATUS2_pcap_dwstm_component_presence(unsigned int upcap_dwstm_component_presence);
int iSetLINK_CTRL_STATUS2_pcap_drs_msg_recved(unsigned int upcap_drs_msg_recved);
int iSetSLOT_CAP_2_pcap_slot_cap_2(unsigned int upcap_slot_cap_2);
int iSetSLOT_CTRL_2_pcap_slot_ctrl_2(unsigned int upcap_slot_ctrl_2);
int iSetMSI_CAP_HEADER_msicap_capability_id(unsigned int umsicap_capability_id);
int iSetMSI_CAP_HEADER_msicap_nxt_ptr(unsigned int umsicap_nxt_ptr);
int iSetMSI_CAP_HEADER_msicap_enable(unsigned int umsicap_enable);
int iSetMSI_CAP_HEADER_msicap_mmc(unsigned int umsicap_mmc);
int iSetMSI_CAP_HEADER_msicap_mme(unsigned int umsicap_mme);
int iSetMSI_CAP_HEADER_msicap_c64(unsigned int umsicap_c64);
int iSetMSI_CAP_HEADER_msicap_pvm(unsigned int umsicap_pvm);
int iSetMSI_CAP_HEADER_msicap_support(unsigned int umsicap_support);
int iSetMSI_ADDR_msicap_0reserved(unsigned int umsicap_0reserved);
int iSetMSI_ADDR_msicap_addr(unsigned int umsicap_addr);
int iSetMSI_UP_ADDR_msicap_uaddr(unsigned int umsicap_uaddr);
int iSetMSI_DATA_msicap_data(unsigned int umsicap_data);
int iSetMSI_DATA_msicap_1reserved(unsigned int umsicap_1reserved);
int iSetMSI_MASK_msicap_mask(unsigned int umsicap_mask);
int iSetMSI_PENDING_msicap_pend(unsigned int umsicap_pend);
int iSetMSIX_CAP_HEADER_msixcap_capability_id(unsigned int umsixcap_capability_id);
int iSetMSIX_CAP_HEADER_msixcap_nxt_ptr(unsigned int umsixcap_nxt_ptr);
int iSetMSIX_CAP_HEADER_msixcap_table_size(unsigned int umsixcap_table_size);
int iSetMSIX_CAP_HEADER_msixcap_0reserved(unsigned int umsixcap_0reserved);
int iSetMSIX_CAP_HEADER_msixcap_func_mask(unsigned int umsixcap_func_mask);
int iSetMSIX_CAP_HEADER_msixcap_enable(unsigned int umsixcap_enable);
int iSetMSIX_TABLE_msixcap_table_bir(unsigned int umsixcap_table_bir);
int iSetMSIX_TABLE_msixcap_table_ofset(unsigned int umsixcap_table_ofset);
int iSetMSIX_PBA_msixcap_pba_bir(unsigned int umsixcap_pba_bir);
int iSetMSIX_PBA_msixcap_pba_ofset(unsigned int umsixcap_pba_ofset);
int iSetPME_CAP_HEADER_pmcap_capability_id(unsigned int upmcap_capability_id);
int iSetPME_CAP_HEADER_pmcap_nxt_ptr(unsigned int upmcap_nxt_ptr);
int iSetPME_CAP_HEADER_pmcap_version(unsigned int upmcap_version);
int iSetPME_CAP_HEADER_pmcap_clk(unsigned int upmcap_clk);
int iSetPME_CAP_HEADER_pmcap_0reserved(unsigned int upmcap_0reserved);
int iSetPME_CAP_HEADER_pmcap_device_spec_ini(unsigned int upmcap_device_spec_ini);
int iSetPME_CAP_HEADER_pmcap_aux_current(unsigned int upmcap_aux_current);
int iSetPME_CAP_HEADER_pmcap_d1_support(unsigned int upmcap_d1_support);
int iSetPME_CAP_HEADER_pmcap_d2_support(unsigned int upmcap_d2_support);
int iSetPME_CAP_HEADER_pmcap_pme_support(unsigned int upmcap_pme_support);
int iSetPME_CTRL_STATUS_pmcap_pwr_state(unsigned int upmcap_pwr_state);
int iSetPME_CTRL_STATUS_pmcap_3reserved(unsigned int upmcap_3reserved);
int iSetPME_CTRL_STATUS_pmcap_no_soft_reset(unsigned int upmcap_no_soft_reset);
int iSetPME_CTRL_STATUS_pmcap_2reserved(unsigned int upmcap_2reserved);
int iSetPME_CTRL_STATUS_pmcap_pme_en(unsigned int upmcap_pme_en);
int iSetPME_CTRL_STATUS_pmcap_data_sel(unsigned int upmcap_data_sel);
int iSetPME_CTRL_STATUS_pmcap_data_scale(unsigned int upmcap_data_scale);
int iSetPME_CTRL_STATUS_pmcap_pme_status(unsigned int upmcap_pme_status);
int iSetPME_CTRL_STATUS_pmcap_1reserved(unsigned int upmcap_1reserved);
int iSetPME_CTRL_STATUS_pmcap_b2_b3_n(unsigned int upmcap_b2_b3_n);
int iSetPME_CTRL_STATUS_pmcap_bpcc_en(unsigned int upmcap_bpcc_en);
int iSetPME_CTRL_STATUS_pmcap_data(unsigned int upmcap_data);
int iSetACS_EXTENDED_CAP_HEADER_acscap_id(unsigned int uacscap_id);
int iSetACS_EXTENDED_CAP_HEADER_acscap_version(unsigned int uacscap_version);
int iSetACS_EXTENDED_CAP_HEADER_acscap_nxt_ptr(unsigned int uacscap_nxt_ptr);
int iSetACS_CTRL_acscap_sv(unsigned int uacscap_sv);
int iSetACS_CTRL_acscap_tb(unsigned int uacscap_tb);
int iSetACS_CTRL_acscap_prr(unsigned int uacscap_prr);
int iSetACS_CTRL_acscap_pcr(unsigned int uacscap_pcr);
int iSetACS_CTRL_acscap_uf(unsigned int uacscap_uf);
int iSetACS_CTRL_acscap_pec(unsigned int uacscap_pec);
int iSetACS_CTRL_acscap_dtp(unsigned int uacscap_dtp);
int iSetACS_CTRL_acscap_1reserved(unsigned int uacscap_1reserved);
int iSetACS_CTRL_acscap_ecvs(unsigned int uacscap_ecvs);
int iSetACS_CTRL_acscap_sv_en(unsigned int uacscap_sv_en);
int iSetACS_CTRL_acscap_tb_en(unsigned int uacscap_tb_en);
int iSetACS_CTRL_acscap_prr_en(unsigned int uacscap_prr_en);
int iSetACS_CTRL_acscap_pcr_en(unsigned int uacscap_pcr_en);
int iSetACS_CTRL_acscap_uf_en(unsigned int uacscap_uf_en);
int iSetACS_CTRL_acscap_pec_en(unsigned int uacscap_pec_en);
int iSetACS_CTRL_acscap_dtp_en(unsigned int uacscap_dtp_en);
int iSetACS_CTRL_acscap_0reserved(unsigned int uacscap_0reserved);
int iSetSRIOV_CAP_HEADER_sriovcap_id(unsigned int usriovcap_id);
int iSetSRIOV_CAP_HEADER_sriovcap_version(unsigned int usriovcap_version);
int iSetSRIOV_CAP_HEADER_sriovcap_nxt_ptr(unsigned int usriovcap_nxt_ptr);
int iSetSRIOV_CAP_sriovcap_vf_mig_cap(unsigned int usriovcap_vf_mig_cap);
int iSetSRIOV_CAP_sriovcap_ari_cap_hier_pres(unsigned int usriovcap_ari_cap_hier_pres);
int iSetSRIOV_CAP_sriovcap_0reserved(unsigned int usriovcap_0reserved);
int iSetSRIOV_CAP_sriovcap_vf_mig_int(unsigned int usriovcap_vf_mig_int);
int iSetSRIOV_CTRL_sriovcap_vf_en(unsigned int usriovcap_vf_en);
int iSetSRIOV_CTRL_sriovcap_vf_mig_en(unsigned int usriovcap_vf_mig_en);
int iSetSRIOV_CTRL_sriovcap_vf_mig_int_en(unsigned int usriovcap_vf_mig_int_en);
int iSetSRIOV_CTRL_sriovcap_vf_mse(unsigned int usriovcap_vf_mse);
int iSetSRIOV_CTRL_sriovcap_ari_cap_hier(unsigned int usriovcap_ari_cap_hier);
int iSetSRIOV_CTRL_sriovcap_2reserved(unsigned int usriovcap_2reserved);
int iSetSRIOV_CTRL_sriovcap_vf_mig_status(unsigned int usriovcap_vf_mig_status);
int iSetSRIOV_CTRL_sriovcap_1reserved(unsigned int usriovcap_1reserved);
int iSetINIT_VF_NUMBER_sriovcap_initial_vf(unsigned int usriovcap_initial_vf);
int iSetINIT_VF_NUMBER_sriovcap_totl_vfs(unsigned int usriovcap_totl_vfs);
int iSetFUNC_DEP_VF_NUM_sriovcap_num_of_vf(unsigned int usriovcap_num_of_vf);
int iSetFUNC_DEP_VF_NUM_sriovcap_func_depen_link(unsigned int usriovcap_func_depen_link);
int iSetFUNC_DEP_VF_NUM_sriovcap_3reserved(unsigned int usriovcap_3reserved);
int iSetVF_RID_SETTING_sriovcap_vf_offset(unsigned int usriovcap_vf_offset);
int iSetVF_RID_SETTING_sriovcap_vf_stride(unsigned int usriovcap_vf_stride);
int iSetVF_DEVICE_ID_sriovcap_4reserved(unsigned int usriovcap_4reserved);
int iSetVF_DEVICE_ID_sriovcap_vf_device_id(unsigned int usriovcap_vf_device_id);
int iSetVF_PAGE_SIZE_sriovcap_support_page_size(unsigned int usriovcap_support_page_size);
int iSetSYSTEM_PAGE_SIZE_sriovcap_sys_page_size(unsigned int usriovcap_sys_page_size);
int iSetVF_BAR0_sriovcap_5reserved(unsigned int usriovcap_5reserved);
int iSetVF_BAR0_sriovcap_vf_bar0_width(unsigned int usriovcap_vf_bar0_width);
int iSetVF_BAR0_sriovcap_vf_bar0_prefetch_en(unsigned int usriovcap_vf_bar0_prefetch_en);
int iSetVF_BAR0_sriovcap_resvd(unsigned int usriovcap_resvd);
int iSetVF_BAR0_sriovcap_vf_bar0_addr(unsigned int usriovcap_vf_bar0_addr);
int iSetVF_BAR1_sriovcap_vf_bar1_addr(unsigned int usriovcap_vf_bar1_addr);
int iSetVF_BAR2_sriovcap_7reserved(unsigned int usriovcap_7reserved);
int iSetVF_BAR2_sriovcap_vf_bar2_width(unsigned int usriovcap_vf_bar2_width);
int iSetVF_BAR2_sriovcap_vf_bar2_prefetch_en(unsigned int usriovcap_vf_bar2_prefetch_en);
int iSetVF_BAR2_sriovcap_resv(unsigned int usriovcap_resv);
int iSetVF_BAR2_sriovcap_vf_bar2_addr(unsigned int usriovcap_vf_bar2_addr);
int iSetVF_BAR3_sriovcap_vf_bar3_addr(unsigned int usriovcap_vf_bar3_addr);
int iSetVF_BAR4_sriovcap_9reserved(unsigned int usriovcap_9reserved);
int iSetVF_BAR4_sriovcap_vf_bar4_width(unsigned int usriovcap_vf_bar4_width);
int iSetVF_BAR4_sriovcap_vf_bar4_prefetch_en(unsigned int usriovcap_vf_bar4_prefetch_en);
int iSetVF_BAR4_sriovcap_vf_bar4_addr(unsigned int usriovcap_vf_bar4_addr);
int iSetVF_BAR5_sriovcap_10reserved(unsigned int usriovcap_10reserved);
int iSetVF_BAR5_sriovcap_vf_bar5_prefetch_en(unsigned int usriovcap_vf_bar5_prefetch_en);
int iSetVF_BAR5_sriovcap_vf_bar5_addr(unsigned int usriovcap_vf_bar5_addr);
int iSetVF_MIG_STATE_ARRAY_sriovcap_vf_mig_state_bir(unsigned int usriovcap_vf_mig_state_bir);
int iSetVF_MIG_STATE_ARRAY_sriovcap_vf_mig_state_offset(unsigned int usriovcap_vf_mig_state_offset);
int iSetTPH_EXTENDED_CAP_HEADER_tphcap_id(unsigned int utphcap_id);
int iSetTPH_EXTENDED_CAP_HEADER_tphcap_version(unsigned int utphcap_version);
int iSetTPH_EXTENDED_CAP_HEADER_tphcap_nxt_ptr(unsigned int utphcap_nxt_ptr);
int iSetTPH_CTRL_tphcap_nsms(unsigned int utphcap_nsms);
int iSetTPH_CTRL_tphcap_ivms(unsigned int utphcap_ivms);
int iSetTPH_CTRL_tphcap_sdms(unsigned int utphcap_sdms);
int iSetTPH_CTRL_tphcap_resvdp0(unsigned int utphcap_resvdp0);
int iSetTPH_CTRL_tphcap_etrs(unsigned int utphcap_etrs);
int iSetTPH_CTRL_tphcap_stl(unsigned int utphcap_stl);
int iSetTPH_CTRL_tphcap_resvdp1(unsigned int utphcap_resvdp1);
int iSetTPH_CTRL_tphcap_st_tbl_size(unsigned int utphcap_st_tbl_size);
int iSetTPH_CTRL_tphcap_resvdp2(unsigned int utphcap_resvdp2);
int iSetTPH_EGRESS_CTRL0_tphcap_sms(unsigned int utphcap_sms);
int iSetTPH_EGRESS_CTRL0_tphcap_resvdp3(unsigned int utphcap_resvdp3);
int iSetTPH_EGRESS_CTRL0_tphcap_tre(unsigned int utphcap_tre);
int iSetTPH_EGRESS_CTRL0_tphcap_resvdp4(unsigned int utphcap_resvdp4);
int iSetPASID_EXTENDED_CAP_HEADER_pasidcap_id(unsigned int upasidcap_id);
int iSetPASID_EXTENDED_CAP_HEADER_pasidcap_version(unsigned int upasidcap_version);
int iSetPASID_EXTENDED_CAP_HEADER_pasidcap_nxt_ptr(unsigned int upasidcap_nxt_ptr);
int iSetPASID_CTRL_pasidcap_resvp0(unsigned int upasidcap_resvp0);
int iSetPASID_CTRL_pasidcap_eps(unsigned int upasidcap_eps);
int iSetPASID_CTRL_pasidcap_pms(unsigned int upasidcap_pms);
int iSetPASID_CTRL_pasidcap_resvp1(unsigned int upasidcap_resvp1);
int iSetPASID_CTRL_pasidcap_mpw(unsigned int upasidcap_mpw);
int iSetPASID_CTRL_pasidcap_resvp2(unsigned int upasidcap_resvp2);
int iSetPASID_CTRL_pasidcap_pasid_en(unsigned int upasidcap_pasid_en);
int iSetPASID_CTRL_pasidcap_epe(unsigned int upasidcap_epe);
int iSetPASID_CTRL_pasidcap_pme(unsigned int upasidcap_pme);
int iSetPASID_CTRL_pasidcap_resvp3(unsigned int upasidcap_resvp3);
int iSetAER_CAP_HEADER_aercap_id(unsigned int uaercap_id);
int iSetAER_CAP_HEADER_aercap_version(unsigned int uaercap_version);
int iSetAER_CAP_HEADER_aercap_nxt_ptr(unsigned int uaercap_nxt_ptr);
int iSetUNCR_ERR_STATUS_aercap_undefined_4(unsigned int uaercap_undefined_4);
int iSetUNCR_ERR_STATUS_aercap_2reserved(unsigned int uaercap_2reserved);
int iSetUNCR_ERR_STATUS_aercap_dl_protocal_err_st(unsigned int uaercap_dl_protocal_err_st);
int iSetUNCR_ERR_STATUS_aercap_sur_down_err_st(unsigned int uaercap_sur_down_err_st);
int iSetUNCR_ERR_STATUS_aercap_1reserved(unsigned int uaercap_1reserved);
int iSetUNCR_ERR_STATUS_aercap_poisoned_tlp_st(unsigned int uaercap_poisoned_tlp_st);
int iSetUNCR_ERR_STATUS_aercap_fc_protocol_err_st(unsigned int uaercap_fc_protocol_err_st);
int iSetUNCR_ERR_STATUS_aercap_cpl_timeeout_st(unsigned int uaercap_cpl_timeeout_st);
int iSetUNCR_ERR_STATUS_aercap_cpl_abort_st(unsigned int uaercap_cpl_abort_st);
int iSetUNCR_ERR_STATUS_aercap_unexp_cpl_st(unsigned int uaercap_unexp_cpl_st);
int iSetUNCR_ERR_STATUS_aercap_rcv_overflow_st(unsigned int uaercap_rcv_overflow_st);
int iSetUNCR_ERR_STATUS_aercap_mal_tlp_st(unsigned int uaercap_mal_tlp_st);
int iSetUNCR_ERR_STATUS_aercap_ecrc_err_st(unsigned int uaercap_ecrc_err_st);
int iSetUNCR_ERR_STATUS_aercap_ur_err_st(unsigned int uaercap_ur_err_st);
int iSetUNCR_ERR_STATUS_aercap_acs_vio_st(unsigned int uaercap_acs_vio_st);
int iSetUNCR_ERR_STATUS_aercap_ue_internal_st(unsigned int uaercap_ue_internal_st);
int iSetUNCR_ERR_STATUS_aercap_mc_blk_st(unsigned int uaercap_mc_blk_st);
int iSetUNCR_ERR_STATUS_aercap_atomicop_eg_blk_st(unsigned int uaercap_atomicop_eg_blk_st);
int iSetUNCR_ERR_STATUS_aercap_tlp_pfx_blk_err_st(unsigned int uaercap_tlp_pfx_blk_err_st);
int iSetUNCR_ERR_STATUS_aercap_0reserved(unsigned int uaercap_0reserved);
int iSetUNCR_ERR_MASK_aercap_undefined_8(unsigned int uaercap_undefined_8);
int iSetUNCR_ERR_MASK_aercap_5reserved(unsigned int uaercap_5reserved);
int iSetUNCR_ERR_MASK_aercap_dl_protocal_err_mask(unsigned int uaercap_dl_protocal_err_mask);
int iSetUNCR_ERR_MASK_aercap_sur_down_err_mask(unsigned int uaercap_sur_down_err_mask);
int iSetUNCR_ERR_MASK_aercap_4reserved(unsigned int uaercap_4reserved);
int iSetUNCR_ERR_MASK_aercap_poisoned_tlp_mask(unsigned int uaercap_poisoned_tlp_mask);
int iSetUNCR_ERR_MASK_aercap_fc_protocol_err_mask(unsigned int uaercap_fc_protocol_err_mask);
int iSetUNCR_ERR_MASK_aercap_cpl_timeeout_mask(unsigned int uaercap_cpl_timeeout_mask);
int iSetUNCR_ERR_MASK_aercap_cpl_abort_mask(unsigned int uaercap_cpl_abort_mask);
int iSetUNCR_ERR_MASK_aercap_unexp_cpl_mask(unsigned int uaercap_unexp_cpl_mask);
int iSetUNCR_ERR_MASK_aercap_rcv_overflow_mask(unsigned int uaercap_rcv_overflow_mask);
int iSetUNCR_ERR_MASK_aercap_mal_tlp_mask(unsigned int uaercap_mal_tlp_mask);
int iSetUNCR_ERR_MASK_aercap_ecrc_err_mask(unsigned int uaercap_ecrc_err_mask);
int iSetUNCR_ERR_MASK_aercap_ur_err_mask(unsigned int uaercap_ur_err_mask);
int iSetUNCR_ERR_MASK_aercap_acs_vio_mask(unsigned int uaercap_acs_vio_mask);
int iSetUNCR_ERR_MASK_aercap_uncor_int_err_mask(unsigned int uaercap_uncor_int_err_mask);
int iSetUNCR_ERR_MASK_aercap_mc_blk_mask(unsigned int uaercap_mc_blk_mask);
int iSetUNCR_ERR_MASK_aercap_atomicop_eg_blk_mask(unsigned int uaercap_atomicop_eg_blk_mask);
int iSetUNCR_ERR_MASK_aercap_tlp_pfx_blk_err_mask(unsigned int uaercap_tlp_pfx_blk_err_mask);
int iSetUNCR_ERR_MASK_aercap_3reserved(unsigned int uaercap_3reserved);
int iSetUNCR_ERR_SEVERITY_aercap_undefined_c(unsigned int uaercap_undefined_c);
int iSetUNCR_ERR_SEVERITY_aercap_8reserved(unsigned int uaercap_8reserved);
int iSetUNCR_ERR_SEVERITY_aercap_dl_protocal_err_ser(unsigned int uaercap_dl_protocal_err_ser);
int iSetUNCR_ERR_SEVERITY_aercap_sur_down_err_ser(unsigned int uaercap_sur_down_err_ser);
int iSetUNCR_ERR_SEVERITY_aercap_7reserved(unsigned int uaercap_7reserved);
int iSetUNCR_ERR_SEVERITY_aercap_poisoned_tlp_ser(unsigned int uaercap_poisoned_tlp_ser);
int iSetUNCR_ERR_SEVERITY_aercap_fc_protocol_err_ser(unsigned int uaercap_fc_protocol_err_ser);
int iSetUNCR_ERR_SEVERITY_aercap_cpl_timeeout_ser(unsigned int uaercap_cpl_timeeout_ser);
int iSetUNCR_ERR_SEVERITY_aercap_cpl_abort_ser(unsigned int uaercap_cpl_abort_ser);
int iSetUNCR_ERR_SEVERITY_aercap_unexp_cpl_ser(unsigned int uaercap_unexp_cpl_ser);
int iSetUNCR_ERR_SEVERITY_aercap_rcv_overflow_ser(unsigned int uaercap_rcv_overflow_ser);
int iSetUNCR_ERR_SEVERITY_aercap_mal_tlp_ser(unsigned int uaercap_mal_tlp_ser);
int iSetUNCR_ERR_SEVERITY_aercap_ecrc_err_ser(unsigned int uaercap_ecrc_err_ser);
int iSetUNCR_ERR_SEVERITY_aercap_ur_err_ser(unsigned int uaercap_ur_err_ser);
int iSetUNCR_ERR_SEVERITY_aercap_acs_vio_ser(unsigned int uaercap_acs_vio_ser);
int iSetUNCR_ERR_SEVERITY_aercap_uncor_int_err_ser(unsigned int uaercap_uncor_int_err_ser);
int iSetUNCR_ERR_SEVERITY_aercap_mc_blk_ser(unsigned int uaercap_mc_blk_ser);
int iSetUNCR_ERR_SEVERITY_aercap_atomicop_eg_blk_ser(unsigned int uaercap_atomicop_eg_blk_ser);
int iSetUNCR_ERR_SEVERITY_aercap_tlp_pfx_blk_err_ser(unsigned int uaercap_tlp_pfx_blk_err_ser);
int iSetUNCR_ERR_SEVERITY_aercap_6reserved(unsigned int uaercap_6reserved);
int iSetCOR_ERR_STATUS_aercap_rx_err_st(unsigned int uaercap_rx_err_st);
int iSetCOR_ERR_STATUS_aercap_11reserved(unsigned int uaercap_11reserved);
int iSetCOR_ERR_STATUS_aercap_bad_tlp_st(unsigned int uaercap_bad_tlp_st);
int iSetCOR_ERR_STATUS_aercap_bad_dllp_st(unsigned int uaercap_bad_dllp_st);
int iSetCOR_ERR_STATUS_aercap_reply_num_rollover_st(unsigned int uaercap_reply_num_rollover_st);
int iSetCOR_ERR_STATUS_aercap_10reserved(unsigned int uaercap_10reserved);
int iSetCOR_ERR_STATUS_aercap_reply_timer_timout_st(unsigned int uaercap_reply_timer_timout_st);
int iSetCOR_ERR_STATUS_aercap_adv_non_fatal_err_st(unsigned int uaercap_adv_non_fatal_err_st);
int iSetCOR_ERR_STATUS_aercap_cor_int_err_st(unsigned int uaercap_cor_int_err_st);
int iSetCOR_ERR_STATUS_aercap_header_log_overflow_st(unsigned int uaercap_header_log_overflow_st);
int iSetCOR_ERR_STATUS_aercap_9reserved(unsigned int uaercap_9reserved);
int iSetCOR_ERR_MASK_aercap_rx_err_mask(unsigned int uaercap_rx_err_mask);
int iSetCOR_ERR_MASK_aercap_14reserved(unsigned int uaercap_14reserved);
int iSetCOR_ERR_MASK_aercap_bad_tlp_mask(unsigned int uaercap_bad_tlp_mask);
int iSetCOR_ERR_MASK_aercap_bad_dllp_mask(unsigned int uaercap_bad_dllp_mask);
int iSetCOR_ERR_MASK_aercap_reply_num_rollover_mask(unsigned int uaercap_reply_num_rollover_mask);
int iSetCOR_ERR_MASK_aercap_13reserved(unsigned int uaercap_13reserved);
int iSetCOR_ERR_MASK_aercap_reply_timer_timout_mask(unsigned int uaercap_reply_timer_timout_mask);
int iSetCOR_ERR_MASK_aercap_adv_non_fatal_err_mask(unsigned int uaercap_adv_non_fatal_err_mask);
int iSetCOR_ERR_MASK_aercap_cor_int_err_mask(unsigned int uaercap_cor_int_err_mask);
int iSetCOR_ERR_MASK_aercap_header_log_overflow_mask(unsigned int uaercap_header_log_overflow_mask);
int iSetCOR_ERR_MASK_aercap_12reserved(unsigned int uaercap_12reserved);
int iSetADVACD_CAP_CTRL_aercap_first_err_ptr(unsigned int uaercap_first_err_ptr);
int iSetADVACD_CAP_CTRL_aercap_ecrc_gen_cap(unsigned int uaercap_ecrc_gen_cap);
int iSetADVACD_CAP_CTRL_aercap_ecrc_gen_en(unsigned int uaercap_ecrc_gen_en);
int iSetADVACD_CAP_CTRL_aercap_ecrc_check_cap(unsigned int uaercap_ecrc_check_cap);
int iSetADVACD_CAP_CTRL_aercap_ecrc_check_en(unsigned int uaercap_ecrc_check_en);
int iSetADVACD_CAP_CTRL_aercap_multi_hdr_rec_cap(unsigned int uaercap_multi_hdr_rec_cap);
int iSetADVACD_CAP_CTRL_aercap_multi_hdr_rec_enable(unsigned int uaercap_multi_hdr_rec_enable);
int iSetADVACD_CAP_CTRL_aercap_tlp_prefix_lor_pre(unsigned int uaercap_tlp_prefix_lor_pre);
int iSetADVACD_CAP_CTRL_aercap_15reserved(unsigned int uaercap_15reserved);
int iSetFIRST_HEADER_LOG_aercap_first_header_log(unsigned int uaercap_first_header_log);
int iSetSECOND_HEADER_LOG_aercap_second_header_log(unsigned int uaercap_second_header_log);
int iSetTHIRD_HEADER_LOG_aercap_third_header_log(unsigned int uaercap_third_header_log);
int iSetFOUR_HEADER_LOG_aercap_four_header_log(unsigned int uaercap_four_header_log);
int iSetRWOT_ERRWR_COMMAND_aercap_cor_err_en(unsigned int uaercap_cor_err_en);
int iSetRWOT_ERRWR_COMMAND_aercap_non_fatal_err_en(unsigned int uaercap_non_fatal_err_en);
int iSetRWOT_ERRWR_COMMAND_aercap_fatal_err_en(unsigned int uaercap_fatal_err_en);
int iSetRWOT_ERRWR_COMMAND_aercap_16reserved(unsigned int uaercap_16reserved);
int iSetRWOT_ERRWR_STATUS_aercap_core_err_rcv(unsigned int uaercap_core_err_rcv);
int iSetRWOT_ERRWR_STATUS_aercap_multi_cor_err_rcv(unsigned int uaercap_multi_cor_err_rcv);
int iSetRWOT_ERRWR_STATUS_aercap_uncor_err_rcv(unsigned int uaercap_uncor_err_rcv);
int iSetRWOT_ERRWR_STATUS_aercap_multi_uncor_err_rcv(unsigned int uaercap_multi_uncor_err_rcv);
int iSetRWOT_ERRWR_STATUS_aercap_first_uncor_err(unsigned int uaercap_first_uncor_err);
int iSetRWOT_ERRWR_STATUS_aercap_non_fatal_msg_rcv(unsigned int uaercap_non_fatal_msg_rcv);
int iSetRWOT_ERRWR_STATUS_aercap_fatal_msg_rcv(unsigned int uaercap_fatal_msg_rcv);
int iSetRWOT_ERRWR_STATUS_aercap_17reserved(unsigned int uaercap_17reserved);
int iSetRWOT_ERRWR_STATUS_aercap_aer_int_number(unsigned int uaercap_aer_int_number);
int iSetERR_SOURCE_IDEN_aercap_err_cor_source(unsigned int uaercap_err_cor_source);
int iSetERR_SOURCE_IDEN_aercap_err_non_cir_source(unsigned int uaercap_err_non_cir_source);
int iSetFIRST_PREFIX_LOG_aercap_first_prefix_log(unsigned int uaercap_first_prefix_log);
int iSetSECOND_PREFIX_LOG_aercap_second_prefix_log(unsigned int uaercap_second_prefix_log);
int iSetTHIRD_PREFIX_LOG_aercap_third_prefix_log(unsigned int uaercap_third_prefix_log);
int iSetFOUR_PREFIX_LOG_aercap_four_prefix_log(unsigned int uaercap_four_prefix_log);
int iSetARI_CAP_HEADER_aricap_id(unsigned int uaricap_id);
int iSetARI_CAP_HEADER_aricap_version(unsigned int uaricap_version);
int iSetARI_CAP_HEADER_aricap_nxt_ptr(unsigned int uaricap_nxt_ptr);
int iSetARI_CTRL_aricap_mfvc_func_grp_cap(unsigned int uaricap_mfvc_func_grp_cap);
int iSetARI_CTRL_aricap_acs_func_grp_cap(unsigned int uaricap_acs_func_grp_cap);
int iSetARI_CTRL_aricap_2reserved(unsigned int uaricap_2reserved);
int iSetARI_CTRL_aricap_nxt_func_num(unsigned int uaricap_nxt_func_num);
int iSetARI_CTRL_aricap_mfvc_func_grp_en(unsigned int uaricap_mfvc_func_grp_en);
int iSetARI_CTRL_aricap_acs_func_grp_en(unsigned int uaricap_acs_func_grp_en);
int iSetARI_CTRL_aricap_1reserved(unsigned int uaricap_1reserved);
int iSetARI_CTRL_aricap_func_group(unsigned int uaricap_func_group);
int iSetARI_CTRL_aricap_0reserved(unsigned int uaricap_0reserved);

/* Define the union csr_vf_pcihdr_id_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_vendor_id : 16; /* [15:0] */
        u32 vf_hdr_device_id : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_id_u;

/* Define the union csr_vf_pcihdr_cmdsts_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_io_space_en : 1;      /* [0] */
        u32 vf_hdr_mem_space_en : 1;     /* [1] */
        u32 vf_hdr_bus_master_en : 1;    /* [2] */
        u32 vf_hdr_special_cycle_en : 1; /* [3] */
        u32 vf_hdr_mem_wr_invld_en : 1;  /* [4] */
        u32 vf_hdr_vga_snoop_en : 1;     /* [5] */
        u32 vf_hdr_parity_err_resp : 1;  /* [6] */
        u32 vf_hdr_idsel_stepping : 1;   /* [7] */
        u32 vf_hdr_serr_en : 1;          /* [8] */
        u32 vf_hdr_fast_b2b_en : 1;      /* [9] */
        u32 vf_hdr_intx_disable : 1;     /* [10] */
        u32 vf_hdr_rved : 8;             /* [18:11] */
        u32 vf_hdr_intx_status : 1;      /* [19] */
        u32 vf_hdr_cap_list : 1;         /* [20] */
        u32 vf_hdr_66mhz_cap : 1;        /* [21] */
        u32 vf_hdr_0reserved : 1;        /* [22] */
        u32 vf_hdr_fastb2b_cap : 1;      /* [23] */
        u32 vf_hdr_mdata_par_err : 1;    /* [24] */
        u32 vf_hdr_devsel_timing : 2;    /* [26:25] */
        u32 vf_hdr_sig_target_abort : 1; /* [27] */
        u32 vf_hdr_rx_target_abort : 1;  /* [28] */
        u32 vf_hdr_rx_master_abort : 1;  /* [29] */
        u32 vf_hdr_rx_sys_err : 1;       /* [30] */
        u32 vf_hdr_deteted_par_err : 1;  /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_cmdsts_u;

/* Define the union csr_vf_pcihdr_clsrev_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_revision_id : 8;     /* [7:0] */
        u32 vf_hdr_program_inf : 8;     /* [15:8] */
        u32 vf_hdr_sub_class_code : 8;  /* [23:16] */
        u32 vf_hdr_base_class_code : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_clsrev_u;

/* Define the union csr_vf_pcihdr_misc_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_cachlie_size : 8;  /* [7:0] */
        u32 vf_hdr_latency_timer : 8; /* [15:8] */
        u32 vf_hdr_header_type : 7;   /* [22:16] */
        u32 vf_hdr_multfunc_dev : 1;  /* [23] */
        u32 vf_hdr_bist_result : 4;   /* [27:24] */
        u32 vf_hdr_1reserved : 2;     /* [29:28] */
        u32 vf_hdr_start_bist : 1;    /* [30] */
        u32 vf_hdr_bist_cap : 1;      /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_misc_u;

/* Define the union csr_vf_pcihdr_bar0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_bar0_type : 1;        /* [0] */
        u32 vf_hdr_3reserved : 1;        /* [1] */
        u32 vf_hdr_bar0_width : 1;       /* [2] */
        u32 vf_hdr_bar0_prefetch_en : 1; /* [3] */
        u32 vf_hdr_2reserved : 12;       /* [15:4] */
        u32 vf_hdr_bar0_addr : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_bar0_u;

/* Define the union csr_vf_pcihdr_bar1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_bar1_addr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_bar1_u;

/* Define the union csr_vf_pcihdr_bar2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_bar2_type : 1;        /* [0] */
        u32 vf_hdr_4reserved : 1;        /* [1] */
        u32 vf_hdr_bar2_width : 1;       /* [2] */
        u32 vf_hdr_bar2_prefetch_en : 1; /* [3] */
        u32 vf_hdr_bar2reserved : 16;    /* [19:4] */
        u32 vf_hdr_bar2_addr : 12;       /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_bar2_u;

/* Define the union csr_vf_pcihdr_bar3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_bar3_addr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_bar3_u;

/* Define the union csr_vf_pcihdr_bar4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_bar4_addr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_bar4_u;

/* Define the union csr_vf_pcihdr_bar5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_bar5_type : 1;        /* [0] */
        u32 vf_hdr_bar5_reserved1 : 1;   /* [1] */
        u32 vf_hdr_bar5_width : 1;       /* [2] */
        u32 vf_hdr_bar5_prefetch_en : 1; /* [3] */
        u32 vf_hdr_bar5reserved : 12;    /* [15:4] */
        u32 vf_hdr_bar5_addr : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_bar5_u;

/* Define the union csr_vf_pcihdr_cbus_ptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_carbus_cis_ptr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_cbus_ptr_u;

/* Define the union csr_vf_pcihdr_subsys_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_sys_vendor_id : 16; /* [15:0] */
        u32 vf_hdr_sub_sys_id : 16;    /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_subsys_u;

/* Define the union csr_vf_pcihdr_exprwm_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_ext_rom_enable : 1;     /* [0] */
        u32 vf_hdr_6reserved : 10;         /* [10:1] */
        u32 vf_hdr_ext_rom_base_addr : 21; /* [31:11] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_exprwm_u;

/* Define the union csr_vf_pcihdr_capptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_cap_ptr : 8;    /* [7:0] */
        u32 vf_hdr_7reserved : 24; /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_capptr_u;

/* Define the union csr_vf_pci_rsvd_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_8reserved : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pci_rsvd_u;

/* Define the union csr_vf_pcihdr_int_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_hdr_int_line : 8;    /* [7:0] */
        u32 vf_hdr_int_pin : 8;     /* [15:8] */
        u32 vf_hdr_3creserved : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcihdr_int_u;

/* Define the union csr_vf_pcie_capability_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_pci_capid : 8;      /* [7:0] */
        u32 vf_pcap_nxt_ptr : 8;        /* [15:8] */
        u32 vf_pcap_pci_cap_ver : 4;    /* [19:16] */
        u32 vf_pcap_port_type : 4;      /* [23:20] */
        u32 vf_pcap_slot_implement : 1; /* [24] */
        u32 vf_pcap_int_msg_num : 5;    /* [29:25] */
        u32 vf_pcap_15reserved : 2;     /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pcie_capability_header_u;

/* Define the union csr_vf_device_capbility_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_max_payload_size_support : 3; /* [2:0] */
        u32 vf_pcap_phanotom_fun_sup : 2;         /* [4:3] */
        u32 vf_pcap_ext_tag_sup : 1;              /* [5] */
        u32 vf_pcap_ep_l0s_accept_lat : 3;        /* [8:6] */
        u32 vf_pcap_ep_l1_accept_lat : 3;         /* [11:9] */
        u32 vf_pcap_undefine_04 : 3;              /* [14:12] */
        u32 vf_pcap_ro_base_err_rpt : 1;          /* [15] */
        u32 vf_pcap_0reserved : 2;                /* [17:16] */
        u32 vf_pcap_cap_slot_pwr_limit_val : 8;   /* [25:18] */
        u32 vf_pcap_cap_slot_pwr_sca : 2;         /* [27:26] */
        u32 vf_pcap_flr_cap : 1;                  /* [28] */
        u32 vf_pcap_16reserved : 3;               /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_device_capbility_u;

/* Define the union csr_vf_device_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_cor_err_rpt_en : 1;      /* [0] */
        u32 vf_pcap_non_fat_rpt_en : 1;      /* [1] */
        u32 vf_pcap_fat_err_rpt_en : 1;      /* [2] */
        u32 vf_pcap_ur_rpt_en : 1;           /* [3] */
        u32 vf_pcap_relax_order_en : 1;      /* [4] */
        u32 vf_pcap_max_payload_size : 3;    /* [7:5] */
        u32 vf_pcap_extend_tag_en : 1;       /* [8] */
        u32 vf_pcap_phatom_func_en : 1;      /* [9] */
        u32 vf_pcap_aux_pwr_pm_en : 1;       /* [10] */
        u32 vf_pcap_no_snoop_en : 1;         /* [11] */
        u32 vf_pcap_max_read_req_size : 3;   /* [14:12] */
        u32 vf_pcap_init_flr_reset_rwwo : 1; /* [15] */
        u32 vf_pcap_cor_err_detect : 1;      /* [16] */
        u32 vf_pcap_non_fata_detect : 1;     /* [17] */
        u32 vf_pcap_fat_err_detect : 1;      /* [18] */
        u32 vf_pcap_ur_detect : 1;           /* [19] */
        u32 vf_pcap_aux_pwr_detect : 1;      /* [20] */
        u32 vf_pcap_tlp_pending : 1;         /* [21] */
        u32 vf_pcap_1reserved : 10;          /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_device_ctrl_status_u;

/* Define the union csr_vf_link_capbility_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_max_link_speed : 4;          /* [3:0] */
        u32 vf_pcap_max_link_width : 6;          /* [9:4] */
        u32 vf_pcap_aspm_sup : 2;                /* [11:10] */
        u32 vf_pcap_l0_exit_lat : 3;             /* [14:12] */
        u32 vf_pcap_l1_exit_lat : 3;             /* [17:15] */
        u32 vf_pcap_clock_pm : 1;                /* [18] */
        u32 vf_pcap_surprise_dn_err_rpt_cap : 1; /* [19] */
        u32 vf_pcap_dl_link_act_rpt_cap : 1;     /* [20] */
        u32 vf_pcap_link_band_notice_cap : 1;    /* [21] */
        u32 vf_pcap_aspm_opt_compliance : 1;     /* [22] */
        u32 vf_pcap_1reserved : 1;               /* [23] */
        u32 vf_pcap_port_num : 8;                /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_link_capbility_u;

/* Define the union csr_vf_link_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_aspm_ctrl : 2;             /* [1:0] */
        u32 vf_pcap_4reserved : 1;             /* [2] */
        u32 vf_pcap_rcb : 1;                   /* [3] */
        u32 vf_pcap_link_disable : 1;          /* [4] */
        u32 vf_pcap_retrain_link : 1;          /* [5] */
        u32 vf_pcap_common_clk_cfg : 1;        /* [6] */
        u32 vf_pcap_extended_sync : 1;         /* [7] */
        u32 vf_pcap_clock_pm_en : 1;           /* [8] */
        u32 vf_pcap_hw_auto_width_dis : 1;     /* [9] */
        u32 vf_pcap_link_band_int_en : 1;      /* [10] */
        u32 vf_pcap_link_auto_band_int_en : 1; /* [11] */
        u32 vf_pcap_3reserved : 4;             /* [15:12] */
        u32 vf_pcap_mac_cur_link_spped : 4;    /* [19:16] */
        u32 vf_pcap_mac_cur_link_width : 6;    /* [25:20] */
        u32 vf_pcap_undefined_12 : 1;          /* [26] */
        u32 vf_pcap_link_training : 1;         /* [27] */
        u32 vf_pcap_slot_clk_cfg : 1;          /* [28] */
        u32 vf_pcap_dl_cfg_link_active : 1;    /* [29] */
        u32 vf_pcap_link_band_status : 1;      /* [30] */
        u32 vf_pcap_link_auto_band_status : 1; /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_link_ctrl_status_u;

/* Define the union csr_vf_slot_capability_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_att_button_pre : 1;       /* [0] */
        u32 vf_pcap_pwr_ctrl_pre : 1;         /* [1] */
        u32 vf_pcap_msl_sensor_pre : 1;       /* [2] */
        u32 vf_pcap_att_indecator_pre : 1;    /* [3] */
        u32 vf_pcap_pwr_indicator_pre : 1;    /* [4] */
        u32 vf_pcap_hot_plug_surprise : 1;    /* [5] */
        u32 vf_pcap_hot_plug_cap : 1;         /* [6] */
        u32 vf_pcap_slot_pwr_limit_val : 8;   /* [14:7] */
        u32 vf_pcap_slot_pwr_limit_scale : 2; /* [16:15] */
        u32 vf_pcap_elec_interlock_pre : 1;   /* [17] */
        u32 vf_pcap_no_comman_cpled_sup : 1;  /* [18] */
        u32 vf_pcap_physical_slot_num : 13;   /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_slot_capability_u;

/* Define the union csr_vf_slot_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_att_buttom_pre_en : 1;      /* [0] */
        u32 vf_pcap_pwr_fault_det_en : 1;       /* [1] */
        u32 vf_pcap_mrl_sensor_change_en : 1;   /* [2] */
        u32 vf_pcap_presence_det_change_en : 1; /* [3] */
        u32 vf_pcap_command_cpled_int_en : 1;   /* [4] */
        u32 vf_pcap_hot_plug_int_en : 1;        /* [5] */
        u32 vf_pcap_att_indicator_ctrl : 2;     /* [7:6] */
        u32 vf_pcap_pwr_indicator_ctrl : 2;     /* [9:8] */
        u32 vf_pcap_pwr_ctrled_ctrl : 1;        /* [10] */
        u32 vf_pcap_elec_interlock_ctrl : 1;    /* [11] */
        u32 vf_pcap_dl_state_change_en : 1;     /* [12] */
        u32 vf_pcap_6reserved : 3;              /* [15:13] */
        u32 vf_pcap_attention_button : 1;       /* [16] */
        u32 vf_pcap_pwr_fault_det : 1;          /* [17] */
        u32 vf_pcap_mrl_sensor_change : 1;      /* [18] */
        u32 vf_pcap_presencd_det_change : 1;    /* [19] */
        u32 vf_pcap_command_cpled : 1;          /* [20] */
        u32 vf_pcap_mrl_sensor_st : 1;          /* [21] */
        u32 vf_pcap_presencd_det_st : 1;        /* [22] */
        u32 vf_pcap_elec_interlock_st : 1;      /* [23] */
        u32 vf_pcap_dl_state_change : 1;        /* [24] */
        u32 vf_pcap_5reserved : 7;              /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_slot_ctrl_status_u;

/* Define the union csr_vf_root_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_7reserved : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_root_ctrl_status_u;

/* Define the union csr_vf_root_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_pme_rid : 16;    /* [15:0] */
        u32 vf_pcap_pme_status : 1;  /* [16] */
        u32 vf_pcap_pme_pending : 1; /* [17] */
        u32 vf_pcap_8reserved : 14;  /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_root_status_u;

/* Define the union csr_vf_device_capability2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_cpl_timeout_range : 4;       /* [3:0] */
        u32 vf_pcap_cpl_timeout_disable_sup : 1; /* [4] */
        u32 vf_pcap_ari_fwd_sup : 1;             /* [5] */
        u32 vf_pcap_atomicop_route_sup : 1;      /* [6] */
        u32 vf_pcap_atomic_32bit_cpl_sup : 1;    /* [7] */
        u32 vf_pcap_atomic_64bit_cpl_sup : 1;    /* [8] */
        u32 vf_pcap_cas_128bit_cpl_sup : 1;      /* [9] */
        u32 vf_pcap_no_roen_prpr_pass : 1;       /* [10] */
        u32 vf_pcap_ltr_mech_sup : 1;            /* [11] */
        u32 vf_pcap_tph_cpl_sup : 2;             /* [13:12] */
        u32 vf_pcap_ln_sys_cls : 2;              /* [15:14] */
        u32 vf_pcap_sup_10bit_cpl_tag : 1;       /* [16] */
        u32 vf_pcap_sup_10bit_req_tag : 1;       /* [17] */
        u32 vf_pcap_obff_sup : 2;                /* [19:18] */
        u32 vf_pcap_ext_fmt_sup : 1;             /* [20] */
        u32 vf_pcap_end_end_pfx_sup : 1;         /* [21] */
        u32 vf_pcap_max_end_end_pfx : 2;         /* [23:22] */
        u32 vf_pcap_9reserved : 7;               /* [30:24] */
        u32 vf_pcap_frs_sup : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_device_capability2_u;

/* Define the union csr_vf_device_ctrl2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_cpl_timeout_value : 4;   /* [3:0] */
        u32 vf_pcap_cpl_timeout_dis : 1;     /* [4] */
        u32 vf_pcap_ari_fwd_en : 1;          /* [5] */
        u32 vf_pcap_atomicop_req_en : 1;     /* [6] */
        u32 vf_pcap_atomicop_egress_blk : 1; /* [7] */
        u32 vf_pcap_ido_req_en : 1;          /* [8] */
        u32 vf_pcap_ido_cpl_en : 1;          /* [9] */
        u32 vf_pcap_ltr_mech_en : 1;         /* [10] */
        u32 vf_pcap_en_10bit_req_tag : 1;    /* [11] */
        u32 vf_pcap_11reserved : 1;          /* [12] */
        u32 vf_pcap_obff_en : 2;             /* [14:13] */
        u32 vf_pcap_end_end_pfx_blk : 1;     /* [15] */
        u32 vf_pcap_10reserved : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_device_ctrl2_u;

/* Define the union csr_vf_link_capability2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_13reserved : 1;               /* [0] */
        u32 vf_pcap_link_speed_sup : 7;           /* [7:1] */
        u32 vf_pcap_cross_link_sup : 1;           /* [8] */
        u32 vf_pcap_cfg_tx_lower_skp_cap : 7;     /* [15:9] */
        u32 vf_pcap_cfg_rx_lower_skp_cap : 7;     /* [22:16] */
        u32 vf_pcap_retimer_presence_detect : 1;  /* [23] */
        u32 vf_pcap_retimer2_presence_detect : 1; /* [24] */
        u32 vf_pcap_12reserved : 6;               /* [30:25] */
        u32 vf_pcap_drs_sup : 1;                  /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_link_capability2_u;

/* Define the union csr_vf_link_ctrl_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_target_link_speed : 4;        /* [3:0] */
        u32 vf_pcap_enter_compliance : 1;         /* [4] */
        u32 vf_pcap_hw_auto_speed_dis : 1;        /* [5] */
        u32 vf_pcap_selectable_de_emphasis : 1;   /* [6] */
        u32 vf_pcap_transmit_margin : 3;          /* [9:7] */
        u32 vf_pcap_enter_mod_compliance : 1;     /* [10] */
        u32 vf_pcap_compliance_sos : 1;           /* [11] */
        u32 vf_pcap_compliance_preset_deemp : 4;  /* [15:12] */
        u32 vf_pcap_cur_deemp_level : 1;          /* [16] */
        u32 vf_pcap_eq_8g_complete : 1;           /* [17] */
        u32 vf_pcap_eq_8g_phase1_success : 1;     /* [18] */
        u32 vf_pcap_eq_8g_phase2_success : 1;     /* [19] */
        u32 vf_pcap_eq_8g_phase3_success : 1;     /* [20] */
        u32 vf_pcap_link_8g_eq_req : 1;           /* [21] */
        u32 vf_pcap_retimer_presence_detect : 1;  /* [22] */
        u32 vf_pcap_retimer2_presence_detect : 1; /* [23] */
        u32 vf_pcap_14reserved : 4;               /* [27:24] */
        u32 vf_pcap_dwstm_component_presence : 1; /* [28] */
        u32 vf_pcap_drs_msg_recved : 3;           /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_link_ctrl_status2_u;

/* Define the union csr_vf_slot_cap_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_slot_cap_2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_slot_cap_2_u;

/* Define the union csr_vf_slot_ctrl_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pcap_slot_ctrl_2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_slot_ctrl_2_u;

/* Define the union csr_vf_msi_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msicap_capability_id : 8; /* [7:0] */
        u32 vf_msicap_nxt_ptr : 8;       /* [15:8] */
        u32 vf_msicap_enable : 1;        /* [16] */
        u32 vf_msicap_mmc : 3;           /* [19:17] */
        u32 vf_msicap_mme : 3;           /* [22:20] */
        u32 vf_msicap_c64 : 1;           /* [23] */
        u32 vf_msicap_pvm : 1;           /* [24] */
        u32 vf_msicap_support : 7;       /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msi_cap_header_u;

/* Define the union csr_vf_msi_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msicap_0reserved : 2; /* [1:0] */
        u32 vf_msicap_addr : 30;     /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msi_addr_u;

/* Define the union csr_vf_msi_up_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msicap_uaddr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msi_up_addr_u;

/* Define the union csr_vf_msi_data_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msicap_data : 16;      /* [15:0] */
        u32 vf_msicap_1reserved : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msi_data_u;

/* Define the union csr_vf_msi_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msicap_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msi_mask_u;

/* Define the union csr_vf_msi_pending_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msicap_pend : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msi_pending_u;

/* Define the union csr_vf_msix_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msixcap_capability_id : 8; /* [7:0] */
        u32 vf_msixcap_nxt_ptr : 8;       /* [15:8] */
        u32 vf_msixcap_table_size : 11;   /* [26:16] */
        u32 vf_msixcap_0reserved : 3;     /* [29:27] */
        u32 vf_msixcap_func_mask : 1;     /* [30] */
        u32 vf_msixcap_enable : 1;        /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msix_cap_header_u;

/* Define the union csr_vf_msix_table_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msixcap_table_bir : 3;    /* [2:0] */
        u32 vf_msixcap_table_ofset : 29; /* [31:3] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msix_table_u;

/* Define the union csr_vf_msix_pba_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_msixcap_pba_bir : 3;    /* [2:0] */
        u32 vf_msixcap_pba_ofset : 29; /* [31:3] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_msix_pba_u;

/* Define the union csr_vf_pme_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pmcap_capability_id : 8;   /* [7:0] */
        u32 vf_pmcap_nxt_ptr : 8;         /* [15:8] */
        u32 vf_pmcap_version : 3;         /* [18:16] */
        u32 vf_pmcap_clk : 1;             /* [19] */
        u32 vf_pmcap_0reserved : 1;       /* [20] */
        u32 vf_pmcap_device_spec_ini : 1; /* [21] */
        u32 vf_pmcap_aux_current : 3;     /* [24:22] */
        u32 vf_pmcap_d1_support : 1;      /* [25] */
        u32 vf_pmcap_d2_support : 1;      /* [26] */
        u32 vf_pmcap_pme_support : 5;     /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pme_cap_header_u;

/* Define the union csr_vf_pme_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_pmcap_pwr_status : 2;    /* [1:0] */
        u32 vf_pmcap_3reserved : 1;     /* [2] */
        u32 vf_pmcap_no_soft_reset : 1; /* [3] */
        u32 vf_pmcap_2reserved : 4;     /* [7:4] */
        u32 vf_pmcap_pme_en : 1;        /* [8] */
        u32 vf_pmcap_data_sel : 4;      /* [12:9] */
        u32 vf_pmcap_data_scale : 2;    /* [14:13] */
        u32 vf_pmcap_pme_status : 1;    /* [15] */
        u32 vf_pmcap_1reserved : 6;     /* [21:16] */
        u32 vf_pmcap_b2_b3_n : 1;       /* [22] */
        u32 vf_pmcap_bpcc_en : 1;       /* [23] */
        u32 vf_pmcap_data : 8;          /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_pme_ctrl_status_u;

/* Define the union csr_vf_acs_extended_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_acscap_id : 16;      /* [15:0] */
        u32 vf_acscap_version : 4;  /* [19:16] */
        u32 vf_acscap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_acs_extended_cap_header_u;

/* Define the union csr_vf_acs_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_acscap_sv : 1;        /* [0] */
        u32 vf_acscap_tb : 1;        /* [1] */
        u32 vf_acscap_prr : 1;       /* [2] */
        u32 vf_acscap_pcr : 1;       /* [3] */
        u32 vf_acscap_uf : 1;        /* [4] */
        u32 vf_acscap_pec : 1;       /* [5] */
        u32 vf_acscap_dtp : 1;       /* [6] */
        u32 vf_acscap_1reserved : 1; /* [7] */
        u32 vf_acscap_ecvs : 8;      /* [15:8] */
        u32 vf_acscap_sv_en : 1;     /* [16] */
        u32 vf_acscap_tb_en : 1;     /* [17] */
        u32 vf_acscap_prr_en : 1;    /* [18] */
        u32 vf_acscap_pcr_en : 1;    /* [19] */
        u32 vf_acscap_uf_en : 1;     /* [20] */
        u32 vf_acscap_pec_en : 1;    /* [21] */
        u32 vf_acscap_dtp_en : 1;    /* [22] */
        u32 vf_acscap_0reserved : 9; /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_acs_ctrl_u;

/* Define the union csr_vf_tph_extended_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_tphcap_id : 16;      /* [15:0] */
        u32 vf_tphcap_version : 4;  /* [19:16] */
        u32 vf_tphcap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_tph_extended_cap_header_u;

/* Define the union csr_vf_tph_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_tphcap_nsms : 1;         /* [0] */
        u32 vf_tphcap_ivms : 1;         /* [1] */
        u32 vf_tphcap_sdms : 1;         /* [2] */
        u32 vf_tphcap_resvdp0 : 5;      /* [7:3] */
        u32 vf_tphcap_etrs : 1;         /* [8] */
        u32 vf_tphcap_stl : 2;          /* [10:9] */
        u32 vf_tphcap_resvdp1 : 5;      /* [15:11] */
        u32 vf_tphcap_st_tbl_size : 11; /* [26:16] */
        u32 vf_tphcap_resvdp2 : 5;      /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_tph_ctrl_u;

/* Define the union csr_vf_tph_egress_ctrl0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_tphcap_sms : 3;      /* [2:0] */
        u32 vf_tphcap_resvdp3 : 5;  /* [7:3] */
        u32 vf_tphcap_tre : 1;      /* [8] */
        u32 vf_tphcap_resvdp4 : 23; /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_tph_egress_ctrl0_u;

/* Define the union csr_vf_ari_cap_header_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_aricap_id : 16;      /* [15:0] */
        u32 vf_aricap_version : 4;  /* [19:16] */
        u32 vf_aricap_nxt_ptr : 12; /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_ari_cap_header_u;

/* Define the union csr_vf_ari_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 vf_aricap_mfvc_func_grp_cap : 1; /* [0] */
        u32 vf_aricap_acs_func_grp_cap : 1;  /* [1] */
        u32 vf_aricap_2reserved : 6;         /* [7:2] */
        u32 vf_aricap_nxt_func_num : 8;      /* [15:8] */
        u32 vf_aricap_mfvc_func_grp_en : 1;  /* [16] */
        u32 vf_aricap_acs_func_grp_en : 1;   /* [17] */
        u32 vf_aricap_1reserved : 2;         /* [19:18] */
        u32 vf_aricap_func_group : 3;        /* [22:20] */
        u32 vf_aricap_0reserved : 9;         /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_vf_ari_ctrl_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_vf_pcihdr_id_u vf_pcihdr_id;                             /* 0 */
    volatile csr_vf_pcihdr_cmdsts_u vf_pcihdr_cmdsts;                     /* 4 */
    volatile csr_vf_pcihdr_clsrev_u vf_pcihdr_clsrev;                     /* 8 */
    volatile csr_vf_pcihdr_misc_u vf_pcihdr_misc;                         /* C */
    volatile csr_vf_pcihdr_bar0_u vf_pcihdr_bar0;                         /* 10 */
    volatile csr_vf_pcihdr_bar1_u vf_pcihdr_bar1;                         /* 14 */
    volatile csr_vf_pcihdr_bar2_u vf_pcihdr_bar2;                         /* 18 */
    volatile csr_vf_pcihdr_bar3_u vf_pcihdr_bar3;                         /* 1C */
    volatile csr_vf_pcihdr_bar4_u vf_pcihdr_bar4;                         /* 20 */
    volatile csr_vf_pcihdr_bar5_u vf_pcihdr_bar5;                         /* 24 */
    volatile csr_vf_pcihdr_cbus_ptr_u vf_pcihdr_cbus_ptr;                 /* 28 */
    volatile csr_vf_pcihdr_subsys_u vf_pcihdr_subsys;                     /* 2C */
    volatile csr_vf_pcihdr_exprwm_u vf_pcihdr_exprwm;                     /* 30 */
    volatile csr_vf_pcihdr_capptr_u vf_pcihdr_capptr;                     /* 34 */
    volatile csr_vf_pci_rsvd_u vf_pci_rsvd;                               /* 38 */
    volatile csr_vf_pcihdr_int_u vf_pcihdr_int;                           /* 3C */
    volatile csr_vf_pcie_capability_header_u vf_pcie_capability_header;   /* 40 */
    volatile csr_vf_device_capbility_u vf_device_capbility;               /* 44 */
    volatile csr_vf_device_ctrl_status_u vf_device_ctrl_status;           /* 48 */
    volatile csr_vf_link_capbility_u vf_link_capbility;                   /* 4C */
    volatile csr_vf_link_ctrl_status_u vf_link_ctrl_status;               /* 50 */
    volatile csr_vf_slot_capability_u vf_slot_capability;                 /* 54 */
    volatile csr_vf_slot_ctrl_status_u vf_slot_ctrl_status;               /* 58 */
    volatile csr_vf_root_ctrl_status_u vf_root_ctrl_status;               /* 5C */
    volatile csr_vf_root_status_u vf_root_status;                         /* 60 */
    volatile csr_vf_device_capability2_u vf_device_capability2;           /* 64 */
    volatile csr_vf_device_ctrl2_u vf_device_ctrl2;                       /* 68 */
    volatile csr_vf_link_capability2_u vf_link_capability2;               /* 6C */
    volatile csr_vf_link_ctrl_status2_u vf_link_ctrl_status2;             /* 70 */
    volatile csr_vf_slot_cap_2_u vf_slot_cap_2;                           /* 74 */
    volatile csr_vf_slot_ctrl_2_u vf_slot_ctrl_2;                         /* 78 */
    volatile csr_vf_msi_cap_header_u vf_msi_cap_header;                   /* 80 */
    volatile csr_vf_msi_addr_u vf_msi_addr;                               /* 84 */
    volatile csr_vf_msi_up_addr_u vf_msi_up_addr;                         /* 88 */
    volatile csr_vf_msi_data_u vf_msi_data;                               /* 8C */
    volatile csr_vf_msi_mask_u vf_msi_mask;                               /* 90 */
    volatile csr_vf_msi_pending_u vf_msi_pending;                         /* 94 */
    volatile csr_vf_msix_cap_header_u vf_msix_cap_header;                 /* A0 */
    volatile csr_vf_msix_table_u vf_msix_table;                           /* A4 */
    volatile csr_vf_msix_pba_u vf_msix_pba;                               /* A8 */
    volatile csr_vf_pme_cap_header_u vf_pme_cap_header;                   /* B0 */
    volatile csr_vf_pme_ctrl_status_u vf_pme_ctrl_status;                 /* B4 */
    volatile csr_vf_acs_extended_cap_header_u vf_acs_extended_cap_header; /* 100 */
    volatile csr_vf_acs_ctrl_u vf_acs_ctrl;                               /* 104 */
    volatile csr_vf_tph_extended_cap_header_u vf_tph_extended_cap_header; /* 300 */
    volatile csr_vf_tph_ctrl_u vf_tph_ctrl;                               /* 304 */
    volatile csr_vf_tph_egress_ctrl0_u vf_tph_egress_ctrl0;               /* 308 */
    volatile csr_vf_ari_cap_header_u vf_ari_cap_header;                   /* 450 */
    volatile csr_vf_ari_ctrl_u vf_ari_ctrl;                               /* 454 */
} S_peh_vf_regs_REGS_TYPE;

/* Declare the struct pointor of the module peh_vf_regs */
extern volatile S_peh_vf_regs_REGS_TYPE *goppeh_vf_regsAllReg;

/* Declare the functions that set the member value */
int iSetVF_PCIHDR_ID_vf_hdr_vendor_id(unsigned int uvf_hdr_vendor_id);
int iSetVF_PCIHDR_ID_vf_hdr_device_id(unsigned int uvf_hdr_device_id);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_io_space_en(unsigned int uvf_hdr_io_space_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_mem_space_en(unsigned int uvf_hdr_mem_space_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_bus_master_en(unsigned int uvf_hdr_bus_master_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_special_cycle_en(unsigned int uvf_hdr_special_cycle_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_mem_wr_invld_en(unsigned int uvf_hdr_mem_wr_invld_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_vga_snoop_en(unsigned int uvf_hdr_vga_snoop_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_parity_err_resp(unsigned int uvf_hdr_parity_err_resp);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_idsel_stepping(unsigned int uvf_hdr_idsel_stepping);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_serr_en(unsigned int uvf_hdr_serr_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_fast_b2b_en(unsigned int uvf_hdr_fast_b2b_en);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_intx_disable(unsigned int uvf_hdr_intx_disable);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_rved(unsigned int uvf_hdr_rved);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_intx_status(unsigned int uvf_hdr_intx_status);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_cap_list(unsigned int uvf_hdr_cap_list);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_66mhz_cap(unsigned int uvf_hdr_66mhz_cap);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_0reserved(unsigned int uvf_hdr_0reserved);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_fastb2b_cap(unsigned int uvf_hdr_fastb2b_cap);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_mdata_par_err(unsigned int uvf_hdr_mdata_par_err);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_devsel_timing(unsigned int uvf_hdr_devsel_timing);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_sig_target_abort(unsigned int uvf_hdr_sig_target_abort);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_rx_target_abort(unsigned int uvf_hdr_rx_target_abort);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_rx_master_abort(unsigned int uvf_hdr_rx_master_abort);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_rx_sys_err(unsigned int uvf_hdr_rx_sys_err);
int iSetVF_PCIHDR_CMDSTS_vf_hdr_deteted_par_err(unsigned int uvf_hdr_deteted_par_err);
int iSetVF_PCIHDR_CLSREV_vf_hdr_revision_id(unsigned int uvf_hdr_revision_id);
int iSetVF_PCIHDR_CLSREV_vf_hdr_program_inf(unsigned int uvf_hdr_program_inf);
int iSetVF_PCIHDR_CLSREV_vf_hdr_sub_class_code(unsigned int uvf_hdr_sub_class_code);
int iSetVF_PCIHDR_CLSREV_vf_hdr_base_class_code(unsigned int uvf_hdr_base_class_code);
int iSetVF_PCIHDR_MISC_vf_hdr_cachlie_size(unsigned int uvf_hdr_cachlie_size);
int iSetVF_PCIHDR_MISC_vf_hdr_latency_timer(unsigned int uvf_hdr_latency_timer);
int iSetVF_PCIHDR_MISC_vf_hdr_header_type(unsigned int uvf_hdr_header_type);
int iSetVF_PCIHDR_MISC_vf_hdr_multfunc_dev(unsigned int uvf_hdr_multfunc_dev);
int iSetVF_PCIHDR_MISC_vf_hdr_bist_result(unsigned int uvf_hdr_bist_result);
int iSetVF_PCIHDR_MISC_vf_hdr_1reserved(unsigned int uvf_hdr_1reserved);
int iSetVF_PCIHDR_MISC_vf_hdr_start_bist(unsigned int uvf_hdr_start_bist);
int iSetVF_PCIHDR_MISC_vf_hdr_bist_cap(unsigned int uvf_hdr_bist_cap);
int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_type(unsigned int uvf_hdr_bar0_type);
int iSetVF_PCIHDR_BAR0_vf_hdr_3reserved(unsigned int uvf_hdr_3reserved);
int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_width(unsigned int uvf_hdr_bar0_width);
int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_prefetch_en(unsigned int uvf_hdr_bar0_prefetch_en);
int iSetVF_PCIHDR_BAR0_vf_hdr_2reserved(unsigned int uvf_hdr_2reserved);
int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_addr(unsigned int uvf_hdr_bar0_addr);
int iSetVF_PCIHDR_BAR1_vf_hdr_bar1_addr(unsigned int uvf_hdr_bar1_addr);
int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_type(unsigned int uvf_hdr_bar2_type);
int iSetVF_PCIHDR_BAR2_vf_hdr_4reserved(unsigned int uvf_hdr_4reserved);
int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_width(unsigned int uvf_hdr_bar2_width);
int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_prefetch_en(unsigned int uvf_hdr_bar2_prefetch_en);
int iSetVF_PCIHDR_BAR2_vf_hdr_bar2reserved(unsigned int uvf_hdr_bar2reserved);
int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_addr(unsigned int uvf_hdr_bar2_addr);
int iSetVF_PCIHDR_BAR3_vf_hdr_bar3_addr(unsigned int uvf_hdr_bar3_addr);
int iSetVF_PCIHDR_BAR4_vf_hdr_bar4_addr(unsigned int uvf_hdr_bar4_addr);
int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_type(unsigned int uvf_hdr_bar5_type);
int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_reserved1(unsigned int uvf_hdr_bar5_reserved1);
int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_width(unsigned int uvf_hdr_bar5_width);
int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_prefetch_en(unsigned int uvf_hdr_bar5_prefetch_en);
int iSetVF_PCIHDR_BAR5_vf_hdr_bar5reserved(unsigned int uvf_hdr_bar5reserved);
int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_addr(unsigned int uvf_hdr_bar5_addr);
int iSetVF_PCIHDR_CBUS_PTR_vf_hdr_carbus_cis_ptr(unsigned int uvf_hdr_carbus_cis_ptr);
int iSetVF_PCIHDR_SUBSYS_vf_hdr_sys_vendor_id(unsigned int uvf_hdr_sys_vendor_id);
int iSetVF_PCIHDR_SUBSYS_vf_hdr_sub_sys_id(unsigned int uvf_hdr_sub_sys_id);
int iSetVF_PCIHDR_EXPRWM_vf_hdr_ext_rom_enable(unsigned int uvf_hdr_ext_rom_enable);
int iSetVF_PCIHDR_EXPRWM_vf_hdr_6reserved(unsigned int uvf_hdr_6reserved);
int iSetVF_PCIHDR_EXPRWM_vf_hdr_ext_rom_base_addr(unsigned int uvf_hdr_ext_rom_base_addr);
int iSetVF_PCIHDR_CAPPTR_vf_hdr_cap_ptr(unsigned int uvf_hdr_cap_ptr);
int iSetVF_PCIHDR_CAPPTR_vf_hdr_7reserved(unsigned int uvf_hdr_7reserved);
int iSetVF_PCI_RSVD_vf_hdr_8reserved(unsigned int uvf_hdr_8reserved);
int iSetVF_PCIHDR_INT_vf_hdr_int_line(unsigned int uvf_hdr_int_line);
int iSetVF_PCIHDR_INT_vf_hdr_int_pin(unsigned int uvf_hdr_int_pin);
int iSetVF_PCIHDR_INT_vf_hdr_3creserved(unsigned int uvf_hdr_3creserved);
int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_pci_capid(unsigned int uvf_pcap_pci_capid);
int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_nxt_ptr(unsigned int uvf_pcap_nxt_ptr);
int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_pci_cap_ver(unsigned int uvf_pcap_pci_cap_ver);
int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_port_type(unsigned int uvf_pcap_port_type);
int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_slot_implement(unsigned int uvf_pcap_slot_implement);
int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_int_msg_num(unsigned int uvf_pcap_int_msg_num);
int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_15reserved(unsigned int uvf_pcap_15reserved);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_max_payload_size_support(unsigned int uvf_pcap_max_payload_size_support);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_phanotom_fun_sup(unsigned int uvf_pcap_phanotom_fun_sup);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_ext_tag_sup(unsigned int uvf_pcap_ext_tag_sup);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_ep_l0s_accept_lat(unsigned int uvf_pcap_ep_l0s_accept_lat);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_ep_l1_accept_lat(unsigned int uvf_pcap_ep_l1_accept_lat);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_undefine_04(unsigned int uvf_pcap_undefine_04);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_ro_base_err_rpt(unsigned int uvf_pcap_ro_base_err_rpt);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_0reserved(unsigned int uvf_pcap_0reserved);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_cap_slot_pwr_limit_val(unsigned int uvf_pcap_cap_slot_pwr_limit_val);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_cap_slot_pwr_sca(unsigned int uvf_pcap_cap_slot_pwr_sca);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_flr_cap(unsigned int uvf_pcap_flr_cap);
int iSetVF_DEVICE_CAPBILITY_vf_pcap_16reserved(unsigned int uvf_pcap_16reserved);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_cor_err_rpt_en(unsigned int uvf_pcap_cor_err_rpt_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_non_fat_rpt_en(unsigned int uvf_pcap_non_fat_rpt_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_fat_err_rpt_en(unsigned int uvf_pcap_fat_err_rpt_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_ur_rpt_en(unsigned int uvf_pcap_ur_rpt_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_relax_order_en(unsigned int uvf_pcap_relax_order_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_max_payload_size(unsigned int uvf_pcap_max_payload_size);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_extend_tag_en(unsigned int uvf_pcap_extend_tag_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_phatom_func_en(unsigned int uvf_pcap_phatom_func_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_aux_pwr_pm_en(unsigned int uvf_pcap_aux_pwr_pm_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_no_snoop_en(unsigned int uvf_pcap_no_snoop_en);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_max_read_req_size(unsigned int uvf_pcap_max_read_req_size);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_init_flr_reset_rwwo(unsigned int uvf_pcap_init_flr_reset_rwwo);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_cor_err_detect(unsigned int uvf_pcap_cor_err_detect);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_non_fata_detect(unsigned int uvf_pcap_non_fata_detect);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_fat_err_detect(unsigned int uvf_pcap_fat_err_detect);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_ur_detect(unsigned int uvf_pcap_ur_detect);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_aux_pwr_detect(unsigned int uvf_pcap_aux_pwr_detect);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_tlp_pending(unsigned int uvf_pcap_tlp_pending);
int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_1reserved(unsigned int uvf_pcap_1reserved);
int iSetVF_LINK_CAPBILITY_vf_pcap_max_link_speed(unsigned int uvf_pcap_max_link_speed);
int iSetVF_LINK_CAPBILITY_vf_pcap_max_link_width(unsigned int uvf_pcap_max_link_width);
int iSetVF_LINK_CAPBILITY_vf_pcap_aspm_sup(unsigned int uvf_pcap_aspm_sup);
int iSetVF_LINK_CAPBILITY_vf_pcap_l0_exit_lat(unsigned int uvf_pcap_l0_exit_lat);
int iSetVF_LINK_CAPBILITY_vf_pcap_l1_exit_lat(unsigned int uvf_pcap_l1_exit_lat);
int iSetVF_LINK_CAPBILITY_vf_pcap_clock_pm(unsigned int uvf_pcap_clock_pm);
int iSetVF_LINK_CAPBILITY_vf_pcap_surprise_dn_err_rpt_cap(unsigned int uvf_pcap_surprise_dn_err_rpt_cap);
int iSetVF_LINK_CAPBILITY_vf_pcap_dl_link_act_rpt_cap(unsigned int uvf_pcap_dl_link_act_rpt_cap);
int iSetVF_LINK_CAPBILITY_vf_pcap_link_band_notice_cap(unsigned int uvf_pcap_link_band_notice_cap);
int iSetVF_LINK_CAPBILITY_vf_pcap_aspm_opt_compliance(unsigned int uvf_pcap_aspm_opt_compliance);
int iSetVF_LINK_CAPBILITY_vf_pcap_1reserved(unsigned int uvf_pcap_1reserved);
int iSetVF_LINK_CAPBILITY_vf_pcap_port_num(unsigned int uvf_pcap_port_num);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_aspm_ctrl(unsigned int uvf_pcap_aspm_ctrl);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_4reserved(unsigned int uvf_pcap_4reserved);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_rcb(unsigned int uvf_pcap_rcb);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_disable(unsigned int uvf_pcap_link_disable);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_retrain_link(unsigned int uvf_pcap_retrain_link);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_common_clk_cfg(unsigned int uvf_pcap_common_clk_cfg);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_extended_sync(unsigned int uvf_pcap_extended_sync);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_clock_pm_en(unsigned int uvf_pcap_clock_pm_en);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_hw_auto_width_dis(unsigned int uvf_pcap_hw_auto_width_dis);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_band_int_en(unsigned int uvf_pcap_link_band_int_en);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_auto_band_int_en(unsigned int uvf_pcap_link_auto_band_int_en);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_3reserved(unsigned int uvf_pcap_3reserved);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_mac_cur_link_spped(unsigned int uvf_pcap_mac_cur_link_spped);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_mac_cur_link_width(unsigned int uvf_pcap_mac_cur_link_width);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_undefined_12(unsigned int uvf_pcap_undefined_12);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_training(unsigned int uvf_pcap_link_training);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_slot_clk_cfg(unsigned int uvf_pcap_slot_clk_cfg);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_dl_cfg_link_active(unsigned int uvf_pcap_dl_cfg_link_active);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_band_status(unsigned int uvf_pcap_link_band_status);
int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_auto_band_status(unsigned int uvf_pcap_link_auto_band_status);
int iSetVF_SLOT_CAPABILITY_vf_pcap_att_button_pre(unsigned int uvf_pcap_att_button_pre);
int iSetVF_SLOT_CAPABILITY_vf_pcap_pwr_ctrl_pre(unsigned int uvf_pcap_pwr_ctrl_pre);
int iSetVF_SLOT_CAPABILITY_vf_pcap_msl_sensor_pre(unsigned int uvf_pcap_msl_sensor_pre);
int iSetVF_SLOT_CAPABILITY_vf_pcap_att_indecator_pre(unsigned int uvf_pcap_att_indecator_pre);
int iSetVF_SLOT_CAPABILITY_vf_pcap_pwr_indicator_pre(unsigned int uvf_pcap_pwr_indicator_pre);
int iSetVF_SLOT_CAPABILITY_vf_pcap_hot_plug_surprise(unsigned int uvf_pcap_hot_plug_surprise);
int iSetVF_SLOT_CAPABILITY_vf_pcap_hot_plug_cap(unsigned int uvf_pcap_hot_plug_cap);
int iSetVF_SLOT_CAPABILITY_vf_pcap_slot_pwr_limit_val(unsigned int uvf_pcap_slot_pwr_limit_val);
int iSetVF_SLOT_CAPABILITY_vf_pcap_slot_pwr_limit_scale(unsigned int uvf_pcap_slot_pwr_limit_scale);
int iSetVF_SLOT_CAPABILITY_vf_pcap_elec_interlock_pre(unsigned int uvf_pcap_elec_interlock_pre);
int iSetVF_SLOT_CAPABILITY_vf_pcap_no_comman_cpled_sup(unsigned int uvf_pcap_no_comman_cpled_sup);
int iSetVF_SLOT_CAPABILITY_vf_pcap_physical_slot_num(unsigned int uvf_pcap_physical_slot_num);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_att_buttom_pre_en(unsigned int uvf_pcap_att_buttom_pre_en);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_fault_det_en(unsigned int uvf_pcap_pwr_fault_det_en);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_mrl_sensor_change_en(unsigned int uvf_pcap_mrl_sensor_change_en);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_presence_det_change_en(unsigned int uvf_pcap_presence_det_change_en);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_command_cpled_int_en(unsigned int uvf_pcap_command_cpled_int_en);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_hot_plug_int_en(unsigned int uvf_pcap_hot_plug_int_en);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_att_indicator_ctrl(unsigned int uvf_pcap_att_indicator_ctrl);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_indicator_ctrl(unsigned int uvf_pcap_pwr_indicator_ctrl);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_ctrled_ctrl(unsigned int uvf_pcap_pwr_ctrled_ctrl);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_elec_interlock_ctrl(unsigned int uvf_pcap_elec_interlock_ctrl);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_dl_state_change_en(unsigned int uvf_pcap_dl_state_change_en);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_6reserved(unsigned int uvf_pcap_6reserved);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_attention_button(unsigned int uvf_pcap_attention_button);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_fault_det(unsigned int uvf_pcap_pwr_fault_det);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_mrl_sensor_change(unsigned int uvf_pcap_mrl_sensor_change);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_presencd_det_change(unsigned int uvf_pcap_presencd_det_change);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_command_cpled(unsigned int uvf_pcap_command_cpled);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_mrl_sensor_st(unsigned int uvf_pcap_mrl_sensor_st);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_presencd_det_st(unsigned int uvf_pcap_presencd_det_st);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_elec_interlock_st(unsigned int uvf_pcap_elec_interlock_st);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_dl_state_change(unsigned int uvf_pcap_dl_state_change);
int iSetVF_SLOT_CTRL_STATUS_vf_pcap_5reserved(unsigned int uvf_pcap_5reserved);
int iSetVF_ROOT_CTRL_STATUS_vf_pcap_7reserved(unsigned int uvf_pcap_7reserved);
int iSetVF_ROOT_STATUS_vf_pcap_pme_rid(unsigned int uvf_pcap_pme_rid);
int iSetVF_ROOT_STATUS_vf_pcap_pme_status(unsigned int uvf_pcap_pme_status);
int iSetVF_ROOT_STATUS_vf_pcap_pme_pending(unsigned int uvf_pcap_pme_pending);
int iSetVF_ROOT_STATUS_vf_pcap_8reserved(unsigned int uvf_pcap_8reserved);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_cpl_timeout_range(unsigned int uvf_pcap_cpl_timeout_range);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_cpl_timeout_disable_sup(unsigned int uvf_pcap_cpl_timeout_disable_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ari_fwd_sup(unsigned int uvf_pcap_ari_fwd_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_atomicop_route_sup(unsigned int uvf_pcap_atomicop_route_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_atomic_32bit_cpl_sup(unsigned int uvf_pcap_atomic_32bit_cpl_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_atomic_64bit_cpl_sup(unsigned int uvf_pcap_atomic_64bit_cpl_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_cas_128bit_cpl_sup(unsigned int uvf_pcap_cas_128bit_cpl_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_no_roen_prpr_pass(unsigned int uvf_pcap_no_roen_prpr_pass);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ltr_mech_sup(unsigned int uvf_pcap_ltr_mech_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_tph_cpl_sup(unsigned int uvf_pcap_tph_cpl_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ln_sys_cls(unsigned int uvf_pcap_ln_sys_cls);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_sup_10bit_cpl_tag(unsigned int uvf_pcap_sup_10bit_cpl_tag);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_sup_10bit_req_tag(unsigned int uvf_pcap_sup_10bit_req_tag);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_obff_sup(unsigned int uvf_pcap_obff_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ext_fmt_sup(unsigned int uvf_pcap_ext_fmt_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_end_end_pfx_sup(unsigned int uvf_pcap_end_end_pfx_sup);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_max_end_end_pfx(unsigned int uvf_pcap_max_end_end_pfx);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_9reserved(unsigned int uvf_pcap_9reserved);
int iSetVF_DEVICE_CAPABILITY2_vf_pcap_frs_sup(unsigned int uvf_pcap_frs_sup);
int iSetVF_DEVICE_CTRL2_vf_pcap_cpl_timeout_value(unsigned int uvf_pcap_cpl_timeout_value);
int iSetVF_DEVICE_CTRL2_vf_pcap_cpl_timeout_dis(unsigned int uvf_pcap_cpl_timeout_dis);
int iSetVF_DEVICE_CTRL2_vf_pcap_ari_fwd_en(unsigned int uvf_pcap_ari_fwd_en);
int iSetVF_DEVICE_CTRL2_vf_pcap_atomicop_req_en(unsigned int uvf_pcap_atomicop_req_en);
int iSetVF_DEVICE_CTRL2_vf_pcap_atomicop_egress_blk(unsigned int uvf_pcap_atomicop_egress_blk);
int iSetVF_DEVICE_CTRL2_vf_pcap_ido_req_en(unsigned int uvf_pcap_ido_req_en);
int iSetVF_DEVICE_CTRL2_vf_pcap_ido_cpl_en(unsigned int uvf_pcap_ido_cpl_en);
int iSetVF_DEVICE_CTRL2_vf_pcap_ltr_mech_en(unsigned int uvf_pcap_ltr_mech_en);
int iSetVF_DEVICE_CTRL2_vf_pcap_en_10bit_req_tag(unsigned int uvf_pcap_en_10bit_req_tag);
int iSetVF_DEVICE_CTRL2_vf_pcap_11reserved(unsigned int uvf_pcap_11reserved);
int iSetVF_DEVICE_CTRL2_vf_pcap_obff_en(unsigned int uvf_pcap_obff_en);
int iSetVF_DEVICE_CTRL2_vf_pcap_end_end_pfx_blk(unsigned int uvf_pcap_end_end_pfx_blk);
int iSetVF_DEVICE_CTRL2_vf_pcap_10reserved(unsigned int uvf_pcap_10reserved);
int iSetVF_LINK_CAPABILITY2_vf_pcap_13reserved(unsigned int uvf_pcap_13reserved);
int iSetVF_LINK_CAPABILITY2_vf_pcap_link_speed_sup(unsigned int uvf_pcap_link_speed_sup);
int iSetVF_LINK_CAPABILITY2_vf_pcap_cross_link_sup(unsigned int uvf_pcap_cross_link_sup);
int iSetVF_LINK_CAPABILITY2_vf_pcap_cfg_tx_lower_skp_cap(unsigned int uvf_pcap_cfg_tx_lower_skp_cap);
int iSetVF_LINK_CAPABILITY2_vf_pcap_cfg_rx_lower_skp_cap(unsigned int uvf_pcap_cfg_rx_lower_skp_cap);
int iSetVF_LINK_CAPABILITY2_vf_pcap_retimer_presence_detect(unsigned int uvf_pcap_retimer_presence_detect);
int iSetVF_LINK_CAPABILITY2_vf_pcap_retimer2_presence_detect(unsigned int uvf_pcap_retimer2_presence_detect);
int iSetVF_LINK_CAPABILITY2_vf_pcap_12reserved(unsigned int uvf_pcap_12reserved);
int iSetVF_LINK_CAPABILITY2_vf_pcap_drs_sup(unsigned int uvf_pcap_drs_sup);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_target_link_speed(unsigned int uvf_pcap_target_link_speed);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_enter_compliance(unsigned int uvf_pcap_enter_compliance);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_hw_auto_speed_dis(unsigned int uvf_pcap_hw_auto_speed_dis);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_selectable_de_emphasis(unsigned int uvf_pcap_selectable_de_emphasis);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_transmit_margin(unsigned int uvf_pcap_transmit_margin);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_enter_mod_compliance(unsigned int uvf_pcap_enter_mod_compliance);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_compliance_sos(unsigned int uvf_pcap_compliance_sos);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_compliance_preset_deemp(unsigned int uvf_pcap_compliance_preset_deemp);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_cur_deemp_level(unsigned int uvf_pcap_cur_deemp_level);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_complete(unsigned int uvf_pcap_eq_8g_complete);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_phase1_success(unsigned int uvf_pcap_eq_8g_phase1_success);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_phase2_success(unsigned int uvf_pcap_eq_8g_phase2_success);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_phase3_success(unsigned int uvf_pcap_eq_8g_phase3_success);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_link_8g_eq_req(unsigned int uvf_pcap_link_8g_eq_req);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_retimer_presence_detect(unsigned int uvf_pcap_retimer_presence_detect);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_retimer2_presence_detect(unsigned int uvf_pcap_retimer2_presence_detect);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_14reserved(unsigned int uvf_pcap_14reserved);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_dwstm_component_presence(unsigned int uvf_pcap_dwstm_component_presence);
int iSetVF_LINK_CTRL_STATUS2_vf_pcap_drs_msg_recved(unsigned int uvf_pcap_drs_msg_recved);
int iSetVF_SLOT_CAP_2_vf_pcap_slot_cap_2(unsigned int uvf_pcap_slot_cap_2);
int iSetVF_SLOT_CTRL_2_vf_pcap_slot_ctrl_2(unsigned int uvf_pcap_slot_ctrl_2);
int iSetVF_MSI_CAP_HEADER_vf_msicap_capability_id(unsigned int uvf_msicap_capability_id);
int iSetVF_MSI_CAP_HEADER_vf_msicap_nxt_ptr(unsigned int uvf_msicap_nxt_ptr);
int iSetVF_MSI_CAP_HEADER_vf_msicap_enable(unsigned int uvf_msicap_enable);
int iSetVF_MSI_CAP_HEADER_vf_msicap_mmc(unsigned int uvf_msicap_mmc);
int iSetVF_MSI_CAP_HEADER_vf_msicap_mme(unsigned int uvf_msicap_mme);
int iSetVF_MSI_CAP_HEADER_vf_msicap_c64(unsigned int uvf_msicap_c64);
int iSetVF_MSI_CAP_HEADER_vf_msicap_pvm(unsigned int uvf_msicap_pvm);
int iSetVF_MSI_CAP_HEADER_vf_msicap_support(unsigned int uvf_msicap_support);
int iSetVF_MSI_ADDR_vf_msicap_0reserved(unsigned int uvf_msicap_0reserved);
int iSetVF_MSI_ADDR_vf_msicap_addr(unsigned int uvf_msicap_addr);
int iSetVF_MSI_UP_ADDR_vf_msicap_uaddr(unsigned int uvf_msicap_uaddr);
int iSetVF_MSI_DATA_vf_msicap_data(unsigned int uvf_msicap_data);
int iSetVF_MSI_DATA_vf_msicap_1reserved(unsigned int uvf_msicap_1reserved);
int iSetVF_MSI_MASK_vf_msicap_mask(unsigned int uvf_msicap_mask);
int iSetVF_MSI_PENDING_vf_msicap_pend(unsigned int uvf_msicap_pend);
int iSetVF_MSIX_CAP_HEADER_vf_msixcap_capability_id(unsigned int uvf_msixcap_capability_id);
int iSetVF_MSIX_CAP_HEADER_vf_msixcap_nxt_ptr(unsigned int uvf_msixcap_nxt_ptr);
int iSetVF_MSIX_CAP_HEADER_vf_msixcap_table_size(unsigned int uvf_msixcap_table_size);
int iSetVF_MSIX_CAP_HEADER_vf_msixcap_0reserved(unsigned int uvf_msixcap_0reserved);
int iSetVF_MSIX_CAP_HEADER_vf_msixcap_func_mask(unsigned int uvf_msixcap_func_mask);
int iSetVF_MSIX_CAP_HEADER_vf_msixcap_enable(unsigned int uvf_msixcap_enable);
int iSetVF_MSIX_TABLE_vf_msixcap_table_bir(unsigned int uvf_msixcap_table_bir);
int iSetVF_MSIX_TABLE_vf_msixcap_table_ofset(unsigned int uvf_msixcap_table_ofset);
int iSetVF_MSIX_PBA_vf_msixcap_pba_bir(unsigned int uvf_msixcap_pba_bir);
int iSetVF_MSIX_PBA_vf_msixcap_pba_ofset(unsigned int uvf_msixcap_pba_ofset);
int iSetVF_PME_CAP_HEADER_vf_pmcap_capability_id(unsigned int uvf_pmcap_capability_id);
int iSetVF_PME_CAP_HEADER_vf_pmcap_nxt_ptr(unsigned int uvf_pmcap_nxt_ptr);
int iSetVF_PME_CAP_HEADER_vf_pmcap_version(unsigned int uvf_pmcap_version);
int iSetVF_PME_CAP_HEADER_vf_pmcap_clk(unsigned int uvf_pmcap_clk);
int iSetVF_PME_CAP_HEADER_vf_pmcap_0reserved(unsigned int uvf_pmcap_0reserved);
int iSetVF_PME_CAP_HEADER_vf_pmcap_device_spec_ini(unsigned int uvf_pmcap_device_spec_ini);
int iSetVF_PME_CAP_HEADER_vf_pmcap_aux_current(unsigned int uvf_pmcap_aux_current);
int iSetVF_PME_CAP_HEADER_vf_pmcap_d1_support(unsigned int uvf_pmcap_d1_support);
int iSetVF_PME_CAP_HEADER_vf_pmcap_d2_support(unsigned int uvf_pmcap_d2_support);
int iSetVF_PME_CAP_HEADER_vf_pmcap_pme_support(unsigned int uvf_pmcap_pme_support);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_pwr_status(unsigned int uvf_pmcap_pwr_status);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_3reserved(unsigned int uvf_pmcap_3reserved);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_no_soft_reset(unsigned int uvf_pmcap_no_soft_reset);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_2reserved(unsigned int uvf_pmcap_2reserved);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_pme_en(unsigned int uvf_pmcap_pme_en);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_data_sel(unsigned int uvf_pmcap_data_sel);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_data_scale(unsigned int uvf_pmcap_data_scale);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_pme_status(unsigned int uvf_pmcap_pme_status);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_1reserved(unsigned int uvf_pmcap_1reserved);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_b2_b3_n(unsigned int uvf_pmcap_b2_b3_n);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_bpcc_en(unsigned int uvf_pmcap_bpcc_en);
int iSetVF_PME_CTRL_STATUS_vf_pmcap_data(unsigned int uvf_pmcap_data);
int iSetVF_ACS_EXTENDED_CAP_HEADER_vf_acscap_id(unsigned int uvf_acscap_id);
int iSetVF_ACS_EXTENDED_CAP_HEADER_vf_acscap_version(unsigned int uvf_acscap_version);
int iSetVF_ACS_EXTENDED_CAP_HEADER_vf_acscap_nxt_ptr(unsigned int uvf_acscap_nxt_ptr);
int iSetVF_ACS_CTRL_vf_acscap_sv(unsigned int uvf_acscap_sv);
int iSetVF_ACS_CTRL_vf_acscap_tb(unsigned int uvf_acscap_tb);
int iSetVF_ACS_CTRL_vf_acscap_prr(unsigned int uvf_acscap_prr);
int iSetVF_ACS_CTRL_vf_acscap_pcr(unsigned int uvf_acscap_pcr);
int iSetVF_ACS_CTRL_vf_acscap_uf(unsigned int uvf_acscap_uf);
int iSetVF_ACS_CTRL_vf_acscap_pec(unsigned int uvf_acscap_pec);
int iSetVF_ACS_CTRL_vf_acscap_dtp(unsigned int uvf_acscap_dtp);
int iSetVF_ACS_CTRL_vf_acscap_1reserved(unsigned int uvf_acscap_1reserved);
int iSetVF_ACS_CTRL_vf_acscap_ecvs(unsigned int uvf_acscap_ecvs);
int iSetVF_ACS_CTRL_vf_acscap_sv_en(unsigned int uvf_acscap_sv_en);
int iSetVF_ACS_CTRL_vf_acscap_tb_en(unsigned int uvf_acscap_tb_en);
int iSetVF_ACS_CTRL_vf_acscap_prr_en(unsigned int uvf_acscap_prr_en);
int iSetVF_ACS_CTRL_vf_acscap_pcr_en(unsigned int uvf_acscap_pcr_en);
int iSetVF_ACS_CTRL_vf_acscap_uf_en(unsigned int uvf_acscap_uf_en);
int iSetVF_ACS_CTRL_vf_acscap_pec_en(unsigned int uvf_acscap_pec_en);
int iSetVF_ACS_CTRL_vf_acscap_dtp_en(unsigned int uvf_acscap_dtp_en);
int iSetVF_ACS_CTRL_vf_acscap_0reserved(unsigned int uvf_acscap_0reserved);
int iSetVF_TPH_EXTENDED_CAP_HEADER_vf_tphcap_id(unsigned int uvf_tphcap_id);
int iSetVF_TPH_EXTENDED_CAP_HEADER_vf_tphcap_version(unsigned int uvf_tphcap_version);
int iSetVF_TPH_EXTENDED_CAP_HEADER_vf_tphcap_nxt_ptr(unsigned int uvf_tphcap_nxt_ptr);
int iSetVF_TPH_CTRL_vf_tphcap_nsms(unsigned int uvf_tphcap_nsms);
int iSetVF_TPH_CTRL_vf_tphcap_ivms(unsigned int uvf_tphcap_ivms);
int iSetVF_TPH_CTRL_vf_tphcap_sdms(unsigned int uvf_tphcap_sdms);
int iSetVF_TPH_CTRL_vf_tphcap_resvdp0(unsigned int uvf_tphcap_resvdp0);
int iSetVF_TPH_CTRL_vf_tphcap_etrs(unsigned int uvf_tphcap_etrs);
int iSetVF_TPH_CTRL_vf_tphcap_stl(unsigned int uvf_tphcap_stl);
int iSetVF_TPH_CTRL_vf_tphcap_resvdp1(unsigned int uvf_tphcap_resvdp1);
int iSetVF_TPH_CTRL_vf_tphcap_st_tbl_size(unsigned int uvf_tphcap_st_tbl_size);
int iSetVF_TPH_CTRL_vf_tphcap_resvdp2(unsigned int uvf_tphcap_resvdp2);
int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_sms(unsigned int uvf_tphcap_sms);
int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_resvdp3(unsigned int uvf_tphcap_resvdp3);
int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_tre(unsigned int uvf_tphcap_tre);
int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_resvdp4(unsigned int uvf_tphcap_resvdp4);
int iSetVF_ARI_CAP_HEADER_vf_aricap_id(unsigned int uvf_aricap_id);
int iSetVF_ARI_CAP_HEADER_vf_aricap_version(unsigned int uvf_aricap_version);
int iSetVF_ARI_CAP_HEADER_vf_aricap_nxt_ptr(unsigned int uvf_aricap_nxt_ptr);
int iSetVF_ARI_CTRL_vf_aricap_mfvc_func_grp_cap(unsigned int uvf_aricap_mfvc_func_grp_cap);
int iSetVF_ARI_CTRL_vf_aricap_acs_func_grp_cap(unsigned int uvf_aricap_acs_func_grp_cap);
int iSetVF_ARI_CTRL_vf_aricap_2reserved(unsigned int uvf_aricap_2reserved);
int iSetVF_ARI_CTRL_vf_aricap_nxt_func_num(unsigned int uvf_aricap_nxt_func_num);
int iSetVF_ARI_CTRL_vf_aricap_mfvc_func_grp_en(unsigned int uvf_aricap_mfvc_func_grp_en);
int iSetVF_ARI_CTRL_vf_aricap_acs_func_grp_en(unsigned int uvf_aricap_acs_func_grp_en);
int iSetVF_ARI_CTRL_vf_aricap_1reserved(unsigned int uvf_aricap_1reserved);
int iSetVF_ARI_CTRL_vf_aricap_func_group(unsigned int uvf_aricap_func_group);
int iSetVF_ARI_CTRL_vf_aricap_0reserved(unsigned int uvf_aricap_0reserved);


#endif // __HVA_PEH_C_UNION_DEFINE_H__
